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Refinado por: Base de dados/Biblioteca: ANTE: Abstracts in New Technology & Engineering remover Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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Pipelined Parallel FFT Architectures via Folding Transformation
Pipelined Parallel FFT Architectures via Folding Transformation
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Pipelined Parallel FFT Architectures via Folding Transformation

Ayinala, M. ; Brown, M. ; Parhi, K. K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1068-1081 [Periódico revisado por pares]

New York, NY: IEEE

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2
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
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GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis

Kai He ; Tan, Sheldon X.-D ; Hai Wang ; Guoyong Shi

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1140-1150 [Periódico revisado por pares]

New York: IEEE

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3
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
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FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

Yao Chen ; Gurumani, Swathi T. ; Yun Liang ; Guofeng Li ; Donghui Guo ; Rupnow, Kyle ; Deming Chen

IEEE transactions on very large scale integration (VLSI) systems, 2016-06, Vol.24 (6), p.2220-2233 [Periódico revisado por pares]

New York: IEEE

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4
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
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Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm

TSAO, Yu-Chi ; CHOI, Ken

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.366-371 [Periódico revisado por pares]

New York, NY: IEEE

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5
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection
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A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection

Kyrkou, C ; Theocharides, T

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1034-1047 [Periódico revisado por pares]

New York, NY: IEEE

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6
Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis
Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis
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Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis

Azarderakhsh, R. ; Reyhani-Masoleh, A.

IEEE transactions on very large scale integration (VLSI) systems, 2012-08, Vol.20 (8), p.1453-1466 [Periódico revisado por pares]

New York, NY: IEEE

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7
A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling
A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling
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A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling

TSAI, Pei-Yun ; LIN, Chung-Yi

IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2290-2302 [Periódico revisado por pares]

New York, NY: IEEE

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8
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model
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SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model

Ying Wang ; Xuegong Zhou ; Lingli Wang ; Jian Yan ; Luk, Wayne ; Chenglian Peng ; Jiarong Tong

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2179-2192 [Periódico revisado por pares]

New York, NY: IEEE

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9
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes
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Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

Wang, Zhongfeng ; Cui, Zhiqiang

IEEE transactions on very large scale integration (VLSI) systems, 2007-01, Vol.15 (1), p.104-114 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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10
Resource-Efficient FPGA Architecture and Implementation of Hough Transform
Resource-Efficient FPGA Architecture and Implementation of Hough Transform
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Resource-Efficient FPGA Architecture and Implementation of Hough Transform

Zhong-Ho Chen ; Su, A. W. Y. ; Ming-Ting Sun

IEEE transactions on very large scale integration (VLSI) systems, 2012-08, Vol.20 (8), p.1419-1428 [Periódico revisado por pares]

New York, NY: IEEE

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