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OPU: An FPGA-Based Overlay Processor for Convolutional Neural NetworksYu, Yunxuan ; Wu, Chen ; Zhao, Tiandong ; Wang, Kun ; He, LeiIEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.35-47 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOICavalcante, Matheus ; Schuiki, Fabian ; Zaruba, Florian ; Schaffner, Michael ; Benini, LucaIEEE transactions on very large scale integration (VLSI) systems, 2020-02, Vol.28 (2), p.530-543 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM ArchitectureKala, S. ; Jose, Babita R. ; Mathew, Jimson ; Nalesh, S.IEEE transactions on very large scale integration (VLSI) systems, 2019-12, Vol.27 (12), p.2816-2828 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray TracingYan, Run ; Su, Yin ; Guo, Hui ; Lu, Yashuai ; Wang, Jin ; Xiao, Nong ; Shen, Li ; Wang, Yongwen ; Huang, LiboIEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.396-400 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol SequencesLiu, Siting ; Han, JieIEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1326-1339 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise ControlShi, Dongyuan ; Gan, Woon-Seng ; He, Jianjun ; Lam, BhanIEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.940-953 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGANadal, Jeremy ; Baghdadi, AmerIEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1141-1151 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Pipelined Parallel FFT Architectures via Folding TransformationAyinala, M. ; Brown, M. ; Parhi, K. K.IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1068-1081 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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A Semiparallel Full-Adder in IMPLY LogicGanjeheizadeh Rohani, Shokat ; Taherinejad, Nima ; Radakovits, DavidIEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.297-301 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level ParallelismLing, Ming ; Lin, Qingde ; Chen, Ruiqi ; Qi, Haimeng ; Lin, Mengru ; Zhu, Yanxiang ; Wu, JianshengIEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.484-497 [Periódico revisado por pares]New York: IEEETexto completo disponível |