Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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1 |
Material Type: Artigo
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0.23-V Sample-Boost-Latch-Based Offset Tolerant Sense AmplifierPatel, Dhruv ; Sachdev, ManojIEEE solid-state circuits letters, 2018-01, Vol.1 (1), p.6-9 [Periódico revisado por pares]IEEETexto completo disponível |
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2 |
Material Type: Ata de Congresso
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0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage schemeYamaoka, M. ; Osada, K. ; Ishibashi, K.2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002, p.170-173Piscataway NJ: IEEETexto completo disponível |
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3 |
Material Type: Ata de Congresso
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1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge ProcessorsWang, Jingcheng ; An, Hyochan ; Zhang, Qirui ; Kim, Hun Seok ; Blaauw, David ; Sylvester, Dennis2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2IEEESem texto completo |
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4 |
Material Type: Ata de Congresso
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1.25 volt, low cost, embedded flash memory for low density applicationsMcPartland, R.J. ; Singh, R.2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.158-161IEEETexto completo disponível |
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5 |
Material Type: Artigo
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1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off ApplicationsBoumchedda, Reda ; Makosiej, Adam ; Noel, Jean-Philippe ; Giraud, Bastien ; Christmann, Jean-Frederic ; Miro-Panades, Ivan ; Ciampolini, Lorenzo ; Royer, Pablo ; Mounet, Christopher ; Turgis, David ; Beigne, EdithIEEE solid-state circuits letters, 2018-09, Vol.1 (9), p.186-189 [Periódico revisado por pares]Piscataway: IEEETexto completo disponível |
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6 |
Material Type: Artigo
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A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM ApplicationsMIN, Young-Jae ; JEONG, Chan-Hui ; KIM, Kyu-Young ; WON HO CHOI ; SON, Jong-Pil ; KIM, Chulwoo ; KIM, Soo-WonIEEE transactions on very large scale integration (VLSI) systems, 2012-08, Vol.20 (8), p.1524-1528 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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7 |
Material Type: Artigo
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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-AssistChien-Yu Lu ; Ching-Te Chuang ; Shyh-Jye Jou ; Ming-Hsien Tu ; Ya-Ping Wu ; Chung-Ping Huang ; Kan, Paul-Sen ; Huan-Shun Huang ; Kuen-Di Lee ; Yung-Shin KaoIEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.958-962 [Periódico revisado por pares]IEEETexto completo disponível |
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8 |
Material Type: Ata de Congresso
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A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOSKumar, Mishal ; Grover, Anuj ; Dikshit, Vivek ; Gupta, Varshita2020 24th International Symposium on VLSI Design and Test (VDAT), 2020, p.1-5IEEESem texto completo |
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9 |
Material Type: Artigo
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A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architectureYamauchi, H. ; Iwata, T. ; Akamatsu, H. ; Matsuzawa, A.IEEE transactions on very large scale integration (VLSI) systems, 1997-12, Vol.5 (4), p.377-387 [Periódico revisado por pares]Piscataway, NJ: IEEETexto completo disponível |
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10 |
Material Type: Artigo
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A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power LinesLu, Lu ; Yoo, Taegeun ; Le, Van Loi ; Kim, Tony Tae-HyoungIEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1345-1356 [Periódico revisado por pares]New York: IEEETexto completo disponível |