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Refinado por: assunto: Artificial Neural Networks remover Algorithms remover assunto: Neural Networks remover Computer Science, Hardware & Architecture remover
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MTHAEL: Cross-Architecture IoT Malware Detection Based on Neural Network Advanced Ensemble Learning
MTHAEL: Cross-Architecture IoT Malware Detection Based on Neural Network Advanced Ensemble Learning
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MTHAEL: Cross-Architecture IoT Malware Detection Based on Neural Network Advanced Ensemble Learning

Vasan, Danish ; Alazab, Mamoun ; Venkatraman, Sitalakshmi ; Akram, Junaid ; Qin, Zheng

IEEE transactions on computers, 2020-11, Vol.69 (11), p.1654-1667 [Periódico revisado por pares]

New York: IEEE

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2
SCANN: Synthesis of Compact and Accurate Neural Networks
SCANN: Synthesis of Compact and Accurate Neural Networks
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SCANN: Synthesis of Compact and Accurate Neural Networks

Hassantabar, Shayan ; Wang, Zeyu ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025 [Periódico revisado por pares]

New York: IEEE

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3
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
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OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

Yu, Yunxuan ; Wu, Chen ; Zhao, Tiandong ; Wang, Kun ; He, Lei

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.35-47 [Periódico revisado por pares]

New York: IEEE

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4
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Chen, Pai-Yu ; Peng, Xiaochen ; Yu, Shimeng

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080 [Periódico revisado por pares]

New York: IEEE

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5
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
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High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Kala, S. ; Jose, Babita R. ; Mathew, Jimson ; Nalesh, S.

IEEE transactions on very large scale integration (VLSI) systems, 2019-12, Vol.27 (12), p.2816-2828 [Periódico revisado por pares]

New York: IEEE

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6
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks
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Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks

Yepez, Juan ; Ko, Seok-Bum

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.853-863 [Periódico revisado por pares]

New York: IEEE

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7
Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs
Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs
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Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs

Liu, Shuanglong ; Fan, Hongxiang ; Ferianc, Martin ; Niu, Xinyu ; Shi, Huifeng ; Luk, Wayne

IEEE transaction on neural networks and learning systems, 2022-08, Vol.33 (8), p.3974-3987

United States: IEEE

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8
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory
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GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory

Chen, Jiaxian ; Lin, Yiquan ; Sun, Kaoyi ; Chen, Jiexin ; Ma, Chenlin ; Mao, Rui ; Wang, Yi

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.3579-3590 [Periódico revisado por pares]

New York: IEEE

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9
Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture
Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture
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Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Yu, Ye ; Li, Yingmin ; Che, Shuai ; Jha, Niraj K. ; Zhang, Weifeng

IEEE transactions on computers, 2021-01, Vol.70 (1), p.45-56 [Periódico revisado por pares]

New York: IEEE

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10
Deep and Shallow Architecture of Multilayer Neural Networks
Deep and Shallow Architecture of Multilayer Neural Networks
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Deep and Shallow Architecture of Multilayer Neural Networks

Chang, Chih-Hung

IEEE transaction on neural networks and learning systems, 2015-10, Vol.26 (10), p.2477-2486

United States: IEEE

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