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3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
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3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Bhoj, Ajay N. ; Joshi, Rajiv V. ; Jha, Niraj K.

IEEE transactions on very large scale integration (VLSI) systems, 2013-11, Vol.21 (11), p.2094-2105 [Periódico revisado por pares]

New York, NY: IEEE

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2
692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS
692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS
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692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS

GOOD, Tim ; BENAISSA, Mohammed

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1753-1757 [Periódico revisado por pares]

New York, NY: Institute of Electrical and Electronics Engineers

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3
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
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81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC

KIM, Donghyun ; KIM, Kwanho ; KIM, Joo-Young ; LEE, Seungjin ; LEE, Se-Joong ; YOO, Hoi-Jun

IEEE transactions on very large scale integration (VLSI) systems, 2009-03, Vol.17 (3), p.370-383 [Periódico revisado por pares]

New York, NY: IEEE

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4
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
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A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency

TSAI, Kun-Hung ; LIU, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.80-88 [Periódico revisado por pares]

New York, NY: IEEE

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5
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
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A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration

Niitsu, K. ; Kawai, S. ; Miura, N. ; Ishikuro, H. ; Kuroda, T.

IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1285-1294 [Periódico revisado por pares]

New York, NY: IEEE

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6
Active Cache Emulator
Active Cache Emulator
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Active Cache Emulator

Nurvitadhi, E. ; Jumnit Hong ; Shih-Lien Lu

IEEE transactions on very large scale integration (VLSI) systems, 2008-03, Vol.16 (3), p.229-240 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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7
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
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Adaptive Cooling of Integrated Circuits Using Digital Microfluidics

Paik, P.Y. ; Pamula, V.K. ; Chakrabarty, K.

IEEE transactions on very large scale integration (VLSI) systems, 2008-04, Vol.16 (4), p.432-443 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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8
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs
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An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Jahinuzzaman, S.M. ; Sharifkhani, M. ; Sachdev, M.

IEEE transactions on very large scale integration (VLSI) systems, 2009-09, Vol.17 (9), p.1187-1195 [Periódico revisado por pares]

New York, NY: IEEE

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9
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
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An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

OK, Sunghwa ; CHUNG, Kyunghoon ; KOO, Jabeom ; KIM, Chulwoo

IEEE transactions on very large scale integration (VLSI) systems, 2010-07, Vol.18 (7), p.1130-1134 [Periódico revisado por pares]

New York, NY: IEEE

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10
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
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An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Henkel, J. ; Ernst, R.

IEEE transactions on very large scale integration (VLSI) systems, 2001-04, Vol.9 (2), p.273-289 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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