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High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications
High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications
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High-performance multilayer WSe2 p-type field effect transistors with Pd contacts for circuit applications

Zhang, Lu ; Zhang, Yadong ; Sun, Xiaoting ; Jia, Kunpeng ; Zhang, Qingzhu ; Wu, Zhenhua ; Yin, Huaxiang

Journal of materials science. Materials in electronics, 2021-07, Vol.32 (13), p.17427-17435 [Periódico revisado por pares]

New York: Springer US

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2
Large memory window with low operating voltages using Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel
Large memory window with low operating voltages using Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel
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Large memory window with low operating voltages using Hf1.5Gd2O6 charge trapping layer and thin MoS2 channel

Zhang, Zhaohao ; Liu, Yaoguang ; Wei, Qianhui ; Zhang, Qingzhu ; Li, Junjie ; Wei, Feng ; Wu, Zhenhua ; Yin, Huaxiang

Electronics Letters, 2021-12, Vol.57 (25), p.992-994 [Periódico revisado por pares]

John Wiley & Sons, Inc

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3
Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs
Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs
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Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs

Cheng, Xiaohong ; Li, Yongliang ; Liu, Haoyan ; Zan, Ying ; Lu, Yihong ; Zhang, Qingzhu ; Li, Junjie ; Du, Anyan ; Wu, Zhenhua ; Luo, Jun ; Wang, Wenwu

Journal of materials science. Materials in electronics, 2020-12, Vol.31 (24), p.22478-22486 [Periódico revisado por pares]

New York: Springer US

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4
Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors
Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors
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Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

Gu, Jie ; Zhang, Qingzhu ; Wu, Zhenhua ; Luo, Yanna ; Cao, Lei ; Cai, Yuwei ; Yao, Jiaxin ; Zhang, Zhaohao ; Xu, Gaobo ; Yin, Huaxiang ; Luo, Jun ; Wang, Wenwu

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.35-39 [Periódico revisado por pares]

New York: IEEE

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5
Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device
Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device
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Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

Zhao, Zhiqian ; Cheng, Xiaohong ; Li, Yongliang ; Zan, Ying ; Liu, Haoyan ; Wang, Guilei ; Du, Anyan ; Li, Junjie ; Zhang, Qingzhu ; Xu, Gaobo ; Ma, Xueli ; Wang, Xiaolei ; Yang, Hong ; Xu, Jing ; Luo, Jun ; Li, JunFeng ; Yin, Huaxiang ; Wang, Wenwu

Journal of materials science. Materials in electronics, 2020-04, Vol.31 (8), p.5854-5860 [Periódico revisado por pares]

New York: Springer US

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6
Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate
Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate
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Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate

Pan, Yu ; Li, Junfeng ; Wang, Wenwu ; Ye, Tianchun ; Yin, Huaxiang ; Huang, Kailiang ; Zhang, Zhaohao ; Zhang, Qingzhu ; Jia, Kunpeng ; Wu, Zhenhua ; Luo, Kun ; Yu, Jiahan

IEEE journal of the Electron Devices Society, 2019, Vol.7, p.483-488 [Periódico revisado por pares]

New York: IEEE

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7
An Ultra-Dense One-Transistor Ternary-Content-Addressable Memory Array Based on Non-Volatile and Ambipolar Fin Field-Effect Transistors
An Ultra-Dense One-Transistor Ternary-Content-Addressable Memory Array Based on Non-Volatile and Ambipolar Fin Field-Effect Transistors
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An Ultra-Dense One-Transistor Ternary-Content-Addressable Memory Array Based on Non-Volatile and Ambipolar Fin Field-Effect Transistors

Zhang, Zhaohao ; Mao, Shujuan ; Xu, Gaobo ; Zhang, Qingzhu ; Wu, Zhenhua ; Yin, Huaxiang ; Ye, Tianchun

IEEE transactions on electron devices, 2023-03, Vol.70 (3), p.1-5 [Periódico revisado por pares]

New York: IEEE

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8
Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond
Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond
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Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Zhang, Xuexiang ; Yao, Jiaxin ; Luo, Yanna ; Cao, Lei ; Zheng, Yantong ; Zhang, Qingzhu ; Wu, Zhenhua ; Yin, Huaxiang

IEEE transactions on electron devices, 2024-03, Vol.71 (3), p.1-8 [Periódico revisado por pares]

New York: IEEE

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9
Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node
Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node
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Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node

Xu, Haoqing ; Yao, Jiaxin ; Yang, Zhizhen ; Cao, Lei ; Zhang, Qingzhu ; Li, Yongliang ; Du, Anyan ; Yin, Huaxiang ; Wu, Zhenhua

IEEE transactions on electron devices, 2023-06, Vol.70 (6), p.1-7 [Periódico revisado por pares]

New York: IEEE

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10
Sub-5-Å La2O3 In Situ Dipole Technique for Large VFB Modulation With EOT Reduction and Improved Interface for HKMG Technology
Sub-5-Å La2O3 In Situ Dipole Technique for Large VFB Modulation With EOT Reduction and Improved Interface for HKMG Technology
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Sub-5-Å La2O3 In Situ Dipole Technique for Large VFB Modulation With EOT Reduction and Improved Interface for HKMG Technology

Wei, Yanzhao ; Yao, Jiaxin ; Zhang, Qingzhu ; Sang, Guanqiao ; Bao, Yunjiao ; Gao, Jianfeng ; Li, Junfeng ; Luo, Jun ; Yin, Huaxiang

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.746-751 [Periódico revisado por pares]

New York: IEEE

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