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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
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An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs

Zhu, Chaoyang ; Huang, Kejie ; Yang, Shuyuan ; Zhu, Ziqi ; Zhang, Hejia ; Shen, Haibin

IEEE transactions on very large scale integration (VLSI) systems, 2020-09, Vol.28 (9), p.1953-1965 [Periódico revisado por pares]

New York: IEEE

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2
An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers
An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers
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An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

Fang, Chao ; Zhou, Aojun ; Wang, Zhongfeng

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1573-1586 [Periódico revisado por pares]

New York: IEEE

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3
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key
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Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key

Sengupta, Anirban ; Chaurasia, Rahul ; Anshul, Aditya

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.1-14 [Periódico revisado por pares]

New York: IEEE

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4
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays
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Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays

Sun, Wenhao ; Liu, Deng ; Zou, Zhiwei ; Sun, Wendi ; Chen, Song ; Kang, Yi

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.470-483 [Periódico revisado por pares]

New York: IEEE

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5
Mixed-Signal Computing for Deep Neural Network Inference
Mixed-Signal Computing for Deep Neural Network Inference
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Mixed-Signal Computing for Deep Neural Network Inference

Murmann, Boris

IEEE transactions on very large scale integration (VLSI) systems, 2021-01, Vol.29 (1), p.3-13 [Periódico revisado por pares]

IEEE

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6
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration
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THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration

Lu, Jinming ; Huang, Jian ; Wang, Zhongfeng

IEEE transactions on very large scale integration (VLSI) systems, 2022-08, Vol.30 (8), p.1034-1046 [Periódico revisado por pares]

IEEE

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7
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
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Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks

Ryu, Sungju ; Oh, Youngtaek ; Kim, Jae-Joon

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2137-2141 [Periódico revisado por pares]

New York: IEEE

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8
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs
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Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs

Wu, Xiao ; Wang, Miaoxin ; Lin, Jun ; Wang, Zhongfeng

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1086-1099 [Periódico revisado por pares]

New York: IEEE

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9
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism
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Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism

Ling, Ming ; Lin, Qingde ; Chen, Ruiqi ; Qi, Haimeng ; Lin, Mengru ; Zhu, Yanxiang ; Wu, Jiansheng

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.484-497 [Periódico revisado por pares]

New York: IEEE

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10
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting
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Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting

Sengupta, Anirban ; Rathor, Mahendra

IEEE transactions on very large scale integration (VLSI) systems, 2020-09, Vol.28 (9), p.1979-1992 [Periódico revisado por pares]

New York: IEEE

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