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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
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OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

Yu, Yunxuan ; Wu, Chen ; Zhao, Tiandong ; Wang, Kun ; He, Lei

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.35-47 [Periódico revisado por pares]

New York: IEEE

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2
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences
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Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences

Liu, Siting ; Han, Jie

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1326-1339 [Periódico revisado por pares]

New York: IEEE

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3
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
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High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Kala, S. ; Jose, Babita R. ; Mathew, Jimson ; Nalesh, S.

IEEE transactions on very large scale integration (VLSI) systems, 2019-12, Vol.27 (12), p.2816-2828 [Periódico revisado por pares]

New York: IEEE

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4
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
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Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI

Cavalcante, Matheus ; Schuiki, Fabian ; Zaruba, Florian ; Schaffner, Michael ; Benini, Luca

IEEE transactions on very large scale integration (VLSI) systems, 2020-02, Vol.28 (2), p.530-543 [Periódico revisado por pares]

New York: IEEE

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5
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
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High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

Lian, Xiaocong ; Liu, Zhenyu ; Song, Zhourui ; Dai, Jiwu ; Zhou, Wei ; Ji, Xiangyang

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1874-1885 [Periódico revisado por pares]

New York: IEEE

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6
Mixed-Signal Computing for Deep Neural Network Inference
Mixed-Signal Computing for Deep Neural Network Inference
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Mixed-Signal Computing for Deep Neural Network Inference

Murmann, Boris

IEEE transactions on very large scale integration (VLSI) systems, 2021-01, Vol.29 (1), p.3-13 [Periódico revisado por pares]

IEEE

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7
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing
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MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing

Yan, Run ; Su, Yin ; Guo, Hui ; Lu, Yashuai ; Wang, Jin ; Xiao, Nong ; Shen, Li ; Wang, Yongwen ; Huang, Libo

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.1-5 [Periódico revisado por pares]

New York: IEEE

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8
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA
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Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

Nadal, Jeremy ; Baghdadi, Amer

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1141-1151 [Periódico revisado por pares]

New York: IEEE

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9
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control
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Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control

Shi, Dongyuan ; Gan, Woon-Seng ; He, Jianjun ; Lam, Bhan

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.940-953 [Periódico revisado por pares]

New York: IEEE

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10
Pipelined Parallel FFT Architectures via Folding Transformation
Pipelined Parallel FFT Architectures via Folding Transformation
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Pipelined Parallel FFT Architectures via Folding Transformation

Ayinala, M. ; Brown, M. ; Parhi, K. K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1068-1081 [Periódico revisado por pares]

New York, NY: IEEE

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