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1
Traffic generation and performance evaluation for mesh-based NoCs
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Ata de Congresso
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Traffic generation and performance evaluation for mesh-based NoCs

Tedesco, Leonel ; Mello, Aline ; Garibotti, Diego ; Calazans, Ney ; Moraes, Fernando

Proceedings of the 18th annual symposium on Integrated circuits and system design, 2005, p.184-189

New York, NY, USA: ACM

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2
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
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Virtual channels in networks on chip: implementation and evaluation on hermes NoC

Mello, Aline ; Tedesco, Leonel ; Calazans, Ney ; Moraes, Fernando

Proceedings of the 18th annual symposium on Integrated circuits and system design, 2005, p.178-183

New York, NY, USA: ACM

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3
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
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Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation

Palma, José Carlos S. ; Marcon, César Augusto M. ; Moraes, Fernando G. ; Calazans, Ney L. V. ; Reis, Ricardo A. L. ; Susin, Altamiro A.

Proceedings of the 18th annual symposium on Integrated circuits and system design, 2005, p.196-201

New York, NY, USA: ACM

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4
Traffic Generation and Performance Evaluation for Mesh-based NoCs
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Ata de Congresso
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Traffic Generation and Performance Evaluation for Mesh-based NoCs

Tedesco, L. ; Mello, A. ; Garibotti, D. ; Calazans, N. ; Moraes, F.

2005 18th Symposium on Integrated Circuits and Systems Design, 2005, p.184-189

IEEE

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5
Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC
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Ata de Congresso
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Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC

Mello, A. ; Tedesco, L. ; Calazans, N. ; Moraes, F.

2005 18th Symposium on Integrated Circuits and Systems Design, 2005, p.178-183

IEEE

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6
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
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MultiNoC: A Multiprocessing System Enabled by a Network on Chip

Mello, Aline ; Moller, Leandro ; Calazans, Ney ; Moraes, Fernando

Design, Automation and Test in Europe, 2005, p.234-239

Washington, DC, USA: IEEE Computer Society

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7
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
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Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Marcon, Cesar ; Calazans, Ney ; Moraes, Fernando ; Susin, Altamiro ; Reis, Igor ; Hessel, Fabiano

Design, Automation and Test in Europe, 2005, p.502-507

Washington, DC, USA: IEEE Computer Society

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8
MAIA - a framework for networks on chip generation and verification
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MAIA - a framework for networks on chip generation and verification

Ost, L. ; Mello, A. ; Palma, J. ; Moraes, F. ; Calazans, N.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.1, p.49-52 Vol. 1

IEEE

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9
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems
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PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems

Carvalho, Ewerson ; Calazans, Ney ; Brião, Eduardo ; Moraes, Fernando

Proceedings of the 17th symposium on Integrated circuits and system design, 2004, p.10-15

New York, NY, USA: ACM

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10
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
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Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs

Moraes, Fernando Gehm ; Mesquita, Daniel ; Palma, Jose Carlos ; Moller, Leandro ; Calazans, Ney

Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003, 2003, p.11122-11122

Washington, DC, USA: IEEE Computer Society

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