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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang, Boqian ; Lu, Zhonghai

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1523-1536 [Periódico revisado por pares]

New York: IEEE

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2
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Sun, Hanbo ; Zhu, Zhenhua ; Wang, Chenyu ; Ning, Xuefei ; Dai, Guohao ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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3
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
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An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

Zulehner, Alwin ; Paler, Alexandru ; Wille, Robert

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236 [Periódico revisado por pares]

New York: IEEE

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4
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Ni, Tianming ; Yao, Yao ; Chang, Hao ; Lu, Lin ; Liang, Huaguo ; Yan, Aibin ; Huang, Zhengfeng ; Wen, Xiaoqing

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951 [Periódico revisado por pares]

New York: IEEE

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5
Hardware/Software Co-Exploration of Neural Architectures
Hardware/Software Co-Exploration of Neural Architectures
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Hardware/Software Co-Exploration of Neural Architectures

Jiang, Weiwen ; Yang, Lei ; Sha, Edwin Hsing-Mean ; Zhuge, Qingfeng ; Gu, Shouzhen ; Dasgupta, Sakyasingha ; Shi, Yiyu ; Hu, Jingtong

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815 [Periódico revisado por pares]

IEEE

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6
Specializing CGRAs for Light-Weight Convolutional Neural Networks
Specializing CGRAs for Light-Weight Convolutional Neural Networks
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Specializing CGRAs for Light-Weight Convolutional Neural Networks

Lee, Jungi ; Lee, Jongeun

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3387-3399 [Periódico revisado por pares]

New York: IEEE

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7
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Akopyan, Filipp ; Sawada, Jun ; Cassidy, Andrew ; Alvarez-Icaza, Rodrigo ; Arthur, John ; Merolla, Paul ; Imam, Nabil ; Nakamura, Yutaka ; Datta, Pallab ; Gi-Joon Nam ; Taba, Brian ; Beakes, Michael ; Brezzo, Bernard ; Kuang, Jente B. ; Manohar, Rajit ; Risk, William P. ; Jackson, Bryan ; Modha, Dharmendra S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-10, Vol.34 (10), p.1537-1557 [Periódico revisado por pares]

New York: IEEE

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8
MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation
MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation
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MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

Tan, Jingweijia ; Chen, Keyu ; Wang, Weiren ; Yan, Kaige ; Wei, Xiaohui

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

New York: IEEE

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9
SCANN: Synthesis of Compact and Accurate Neural Networks
SCANN: Synthesis of Compact and Accurate Neural Networks
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SCANN: Synthesis of Compact and Accurate Neural Networks

Hassantabar, Shayan ; Wang, Zeyu ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025 [Periódico revisado por pares]

New York: IEEE

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10
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
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Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

Wijtvliet, M. ; Kumar, A. ; Corporaal, H.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2915-2928 [Periódico revisado por pares]

IEEE

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