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MACACO: modeling and analysis of circuits for approximate computing
MACACO: modeling and analysis of circuits for approximate computing
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

MACACO: modeling and analysis of circuits for approximate computing

Venkatesan, Rangharajan ; Agarwal, Amit ; Roy, Kaushik ; Raghunathan, Anand

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011, p.667-673

IEEE Press

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DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes

Venkatesan, Rangharajan ; Sharad, Mrigank ; Roy, Kaushik ; Raghunathan, Anand

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1825-1830

EDA Consortium

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3
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

Parashar, Angshuman ; Raina, Priyanka ; Shao, Yakun Sophia ; Chen, Yu-Hsin ; Ying, Victor A. ; Mukkara, Anurag ; Venkatesan, Rangharajan ; Khailany, Brucek ; Keckler, Stephen W. ; Emer, Joel

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019, p.304-315

IEEE

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4
Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Material Type:
Artigo 		Adicionar ao Meu Espaço

Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Fong, Xuanyao ; Kim, Yusung ; Venkatesan, Rangharajan ; Choday, Sri Harsha ; Raghunathan, Anand ; Roy, Kaushik

Proceedings of the IEEE, 2016-07, Vol.104 (7), p.1449-1488 [Periódico revisado por pares]

New York: IEEE

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5
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes

Ranjan, Ashish ; Ramasubramanian, Shankar ; Venkatesan, Rangharajan ; Pai, Vijay ; Roy, Kaushik ; Raghunathan, Anand

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, p.181-186

EDA Consortium

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6
SCNN: An accelerator for compressed-sparse convolutional neural networks
SCNN: An accelerator for compressed-sparse convolutional neural networks
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

SCNN: An accelerator for compressed-sparse convolutional neural networks

Parashar, Angshuman ; Minsoo Rhu ; Mukkara, Anurag ; Puglielli, Antonio ; Venkatesan, Rangharajan ; Khailany, Brucek ; Emer, Joel ; Keckler, Stephen W. ; Dally, William J.

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.27-40

ACM

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7
Accelerating Chip Design With Machine Learning
Accelerating Chip Design With Machine Learning
Material Type:
Artigo 		Adicionar ao Meu Espaço

Accelerating Chip Design With Machine Learning

Khailany, Brucek ; Ren, Haoxing ; Dai, Steve ; Godil, Saad ; Keller, Ben ; Kirby, Robert ; Klinefelter, Alicia ; Venkatesan, Rangharajan ; Zhang, Yanqing ; Catanzaro, Bryan ; Dally, William J.

IEEE MICRO, 2020-11, Vol.40 (6), p.23-32 [Periódico revisado por pares]

IEEE

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8
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
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Artigo 		Adicionar ao Meu Espaço

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Zimmer, Brian ; Venkatesan, Rangharajan ; Shao, Yakun Sophia ; Clemons, Jason ; Fojtik, Matthew ; Jiang, Nan ; Keller, Ben ; Klinefelter, Alicia ; Pinckney, Nathaniel ; Raina, Priyanka ; Tell, Stephen G. ; Zhang, Yanqing ; Dally, William J. ; Emer, Joel S. ; Gray, C. Thomas ; Keckler, Stephen W. ; Khailany, Brucek

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932 [Periódico revisado por pares]

New York: IEEE

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9
Efficient Transformer Inference with Statically Structured Sparse Attention
Efficient Transformer Inference with Statically Structured Sparse Attention
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Efficient Transformer Inference with Statically Structured Sparse Attention

Dai, Steve ; Genc, Hasan ; Venkatesan, Rangharajan ; Khailany, Brucek

2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, p.1-6

IEEE

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10
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
Material Type:
Artigo 		Adicionar ao Meu Espaço

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm

Keller, Ben ; Venkatesan, Rangharajan ; Dai, Steve ; Tell, Stephen G. ; Zimmer, Brian ; Sakr, Charbel ; Dally, William J. ; Gray, C. Thomas ; Khailany, Brucek

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1-13 [Periódico revisado por pares]

New York: IEEE

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