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Value prediction for speculative multithreaded architectures

Marcuello, P. ; Tubella, J. ; Gonzalez, A.

MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.230-236

IEEE

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Título:
Value prediction for speculative multithreaded architectures
Autor: Marcuello, P. ; Tubella, J. ; Gonzalez, A.
Assuntos: Arquitectura de computadors ; Computer architecture ; Hardware ; History ; Informàtica ; Microarchitecture ; Multi-threading ; Multiprocessadors ; Parallel architectures ; Parallel processing (Electronic computers) ; Processament en paral·lel (Ordinadors) ; Proposals ; Simultaneous multithreading processors ; Size control ; Yarn ; Àrees temàtiques de la UPC
É parte de: MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.230-236
Descrição: The speculative multithreading paradigm (speculative thread-level parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitectures that adopt this paradigm strongly depends on the performance of the control and data speculation techniques. While control speculation is used to predict the most effective points where a thread can be spawned, data speculation is required to eliminate the serialization imposed by inter-thread dependences. This work studies the performance of different value predictors for speculative multithreaded processors. We propose a value predictor, the increment predictor, and evaluate its performance for a particular microarchitecture that implements this execution paradigm (Clustered Speculative Multithreaded architecture). The proposed trace-oriented increment predictor clearly outperforms trace-adapted versions of the last value, stride and context-based predictors, specially for small-sized history tables. A 1-KB increment predictor achieves a 73% prediction accuracy and a performance that is just 13% lower than that of a perfect value predictor.
Editor: IEEE
Idioma: Inglês

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Value prediction for speculative multithreaded architectures

Marcuello, P. ; Tubella, J. ; Gonzalez, A.

IEEE

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