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Improved shallow trench isolation for sub-halfmicron CMOS

Cabanal, J.P. ; Haond, M.

ESSDERC '91: 21st European Solid State Device Research Conference, 1991, Vol.15 (1), p.651-654 [Periódico revisado por pares]

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Título:
Improved shallow trench isolation for sub-halfmicron CMOS
Autor: Cabanal, J.P. ; Haond, M.
Assuntos: Circuits ; CMOS process ; Design engineering ; Etching ; Microelectronic implants ; MOS devices ; MOSFETs ; Resists ; Standards publication ; Transistors
É parte de: ESSDERC '91: 21st European Solid State Device Research Conference, 1991, Vol.15 (1), p.651-654
Notas: SourceType-Scholarly Journals-2
ObjectType-Feature-2
ObjectType-Conference Paper-1
content type line 23
SourceType-Conference Papers & Proceedings-1
ObjectType-Article-3
Descrição: This paper presents new results on shallow trench isolation with the use of tilted field implants for avoiding the field parasitic transistors. Isolation results and gate oxide breakdown voltage are presented and discussed. The fabrication of 0.7 μm DLM 16K SRAMs with this type of isolation has been demonstrated with results similar to standard isolation circuits.
Editor: Elsevier B.V
Idioma: Inglês

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