A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

Chen, Poki ; Hsiao, Ya-Yun ; Chung, Yi-Su ; Tsai, Wei Xiang ; Lin, Jhih-Min

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.114-124 [Periódico revisado por pares]

New York: IEEE

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