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A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL

Chou, Ming-Han ; Liu, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2474-2478 [Periódico revisado por pares]

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Título:
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL
Autor: Chou, Ming-Han ; Liu, Shen-Iuan
Assuntos: Calibration ; CMOS ; Jitter ; Locking ; Phase detectors ; Phase locked loops ; Phase noise ; Phase-locked loop (PLL) ; Power consumption ; subharmonically injection-locked ; Timing ; timing-adjusted phase detector (TPD) ; type-I ; Vibration ; Voltage measurement ; Voltage-controlled oscillators
É parte de: IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2474-2478
Descrição: A 2.4-GHz area-efficient and fast-locking subharmonically injection-locked type-I phase-locked loop (SIL-TPLL) is presented. A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45-nm CMOS technology. Its active area is 0.013 mm 2 . The power consumption is 5.6 mW at 2.4 GHz for a supply of 0.87 V. The integrated jitter of the SIL-TPLL over 1 kHz to 40 MHz is 0.91 ps.
Editor: New York: IEEE
Idioma: Inglês

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