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Dynamically adaptive register file architecture for energy reduction in embedded processors

Khavari Tavana, Mohammad ; Ahmadian Khameneh, Saba ; Goudarzi, Maziar

Microprocessors and microsystems, 2015-03, Vol.39 (2), p.49-63 [Periódico revisado por pares]

Elsevier B.V

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  • Título:
    Dynamically adaptive register file architecture for energy reduction in embedded processors
  • Autor: Khavari Tavana, Mohammad ; Ahmadian Khameneh, Saba ; Goudarzi, Maziar
  • Assuntos: Architecture (computers) ; Dynamics ; Embedded computer systems ; Embedded systems ; Energy efficiency ; Low-power ; Microprocessors ; Power consumption ; Processor architectures ; Recharging ; Reduction ; Register file ; Registers
  • É parte de: Microprocessors and microsystems, 2015-03, Vol.39 (2), p.49-63
  • Notas: ObjectType-Article-1
    SourceType-Scholarly Journals-1
    ObjectType-Feature-2
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  • Descrição: Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme increases register file area by 3.6% and imposes 2.85% performance overhead on average. Our experimental results on OpenRISC 1200 processor and with selected MiBench benchmark suite show up to 29%, and 54% (24% and 49% on average) reduction in dynamic and static energy consumption of the register file, respectively.
  • Editor: Elsevier B.V
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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