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Analog Performance of Gate-Source/Drain Underlap Triple-Gate SOI nMOSFET

Santos, Sara D. ; Nicoletti, Talitha ; Martino, João A.

ECS transactions, 2011, Vol.39 (1), p.239-246

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Título:
Analog Performance of Gate-Source/Drain Underlap Triple-Gate SOI nMOSFET
Autor: Santos, Sara D. ; Nicoletti, Talitha ; Martino, João A.
É parte de: ECS transactions, 2011, Vol.39 (1), p.239-246
Descrição: The electrical characteristics of triple-gate SOI nMOSFET with gate-source/drain underlap are studied in this paper, focusing on the main analog parameters through 3D numerical simulations.The use of underlap has been reported as one alternative to avoid short channel effects mainly in non-planar transistors. The results indicate that in spite of the underlapped devices show lower drain current (IDS) and transconductance (gm), superior characteristics are achieved in terms of transistor efficiency (gm/IDS ratio), output conductance (gD), Early voltage (VEA) and intrinsic voltage gain (AV) which are required for analog applications.
Idioma: Inglês

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