Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Kim, Jinwoo ; Murali, Gauthaman ; Park, Heechun ; Qin, Eric ; Kwon, Hyoukjun ; Chekuri, Venkata Chaitanya Krishna ; Rahman, Nael Mizanur ; Dasari, Nihar ; Singh, Arvind ; Lee, Minah ; Torun, Hakki Mert ; Roy, Kallol ; Swaminathan, Madhavan ; Mukhopadhyay, Saibal ; Krishna, Tushar ; Lim, Sung Kyu

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2424-2437 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível