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0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

Kumar, Dhirendra ; Anand, Rahul ; Singh, Sajai Vir ; Misra, Prasanna Kumar ; Srivastava, Ashok ; Goswami, Manish

IET circuits, devices & systems, 2020-10, Vol.14 (7), p.1001-1011 [Periódico revisado por pares]

The Institution of Engineering and Technology

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Título:
0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology
Autor: Kumar, Dhirendra ; Anand, Rahul ; Singh, Sajai Vir ; Misra, Prasanna Kumar ; Srivastava, Ashok ; Goswami, Manish
Assuntos: binary format ; bit rate 1.5 Gbit/s ; Cadence Virtuoso tool ; Chi‐square test ; CMOS logic circuits ; CMOS technology environment ; current starved inverter ; current starved topology ; frequency dividers ; generated random numbers ; generated random signals ; high‐frequency divider block ; jitter extraction ; jitter metastability ; Kolmogorov–Smirnov test ; logic design ; logic gates ; Matlab ; metastable block ; NIST 800.22 statistical test suite ; oscillators ; parametric analysis ; post‐layout simulation ; power 0.4 mW ; power dissipation ; random number generation ; Research Article ; ring oscillator ; sampling blocks ; size 180.0 nm ; speed dissipation ; statistical testing ; timing jitter ; TRNG design ; true random number generator
É parte de: IET circuits, devices & systems, 2020-10, Vol.14 (7), p.1001-1011
Descrição: This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.
Editor: The Institution of Engineering and Technology
Idioma: Inglês

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0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

Kumar, Dhirendra ; Anand, Rahul ; Singh, Sajai Vir ; Misra, Prasanna Kumar ; Srivastava, Ashok ; Goswami, Manish

The Institution of Engineering and Technology

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