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0.15-μm n-n gate CMOS technology with channel selective epitaxy and transient enhanced diffusion suppression

Abiko, Hitoshi ; Ono, Atsuki ; Ueno, Ryuuichi ; Masuoka, Sadaaki ; Shishiguchi, Seiichi ; Nakajima, Ken ; Sakai, Isami

Electronics & communications in Japan. Part 2, Electronics, 1996, Vol.79 (11), p.28-35 [Periódico revisado por pares]

New York: Wiley Subscription Services, Inc., A Wiley Company

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  • Título:
    0.15-μm n-n gate CMOS technology with channel selective epitaxy and transient enhanced diffusion suppression
  • Autor: Abiko, Hitoshi ; Ono, Atsuki ; Ueno, Ryuuichi ; Masuoka, Sadaaki ; Shishiguchi, Seiichi ; Nakajima, Ken ; Sakai, Isami
  • Assuntos: 0.15-μm n-n gate CMOS ; SD enhancement ; selective epitaxial growth ; Ti silicide ; transient enhanced diffusion suppression
  • É parte de: Electronics & communications in Japan. Part 2, Electronics, 1996, Vol.79 (11), p.28-35
  • Notas: ark:/67375/WNG-QMCNK0ZK-F
    ArticleID:ECJB4420791104
    istex:554B838BDFEAFA2CECD92194DE8257AFA318BD8D
    Graduated from a master's course at Waseda University, Department of Physics. He then joined NEC. Since then, he has been engaged in research and development of submicron pattern formation technology by electron beam direct writing. He is a manager in the fine fabrication technology development department, ULSI Device Development Laboratory. He is a member of the Applied Physics Society.
    Graduated from the Tokyo Institute of Technology, Department of Electronphysics, in 1992 and completed a master's course in 1994. He then joined NEC. Since then, he has been engaged in device design of deep, submicron CMOS. Presently, he is in the logic development department, ULSI Device Development Laboratory.
    Graduated from Hiroshima University, Department of Electronic Engineering, in 1978 and completed a master's course in 1980. In that year, he joined NEC. Since then, he has been engaged in CMOS device/process development. Presently, he is chief of the logic development department, ULSI Device Development Laboratory. He is a member of the IEEE Electron Devices Society.
    Graduated from a master's course at Aoyama Gakuin University, Department of Physical Engineering, in 1991 (majoring in chemistry). In that year, he joined NEC Information Systems. He has been engaged in the development of CMOS devices by using the process/device simulator. Presently, he is in the science and technology department, Computing Systems Division.
    Graduated from Muroran Institute of Technology, Department of Electronic Engineering, in 1982 and joined NEC. Since then, he has been engaged in CMOS process/device development and circuit design. Presently, he is a manager in the logic department, ULSI Device Development Laboratory.
    Graduated from Tokyo Institute of Technology, Department of Electrophysics, in 1987 and completed a master's course in 1989. In 1992, he completed a doctoral course at the same university. In that year, he joined NEC. Since then, he has been engaged in high‐speed CMOS device development. Presently, he is a manager in the logic department. ULSI Device Development Laboratory. He is a member of the Applied Physics Society.
    Graduated from the Tokyo Institute of Technology, Department of Inorganic Science, in 1984. In 1986, he completed a master's course on material science. He then joined NEC. Presently, he is a manager in the crystal development department, ULSI Development Laboratory. He has been engaged in research and development of the Si‐CVD process. He is a member of the Applied Physics Society and the Japan Physical Society.
  • Descrição: An n‐n gate CMOS process with a minimum gate length of 0.15 μm was developed. By means of the epitaxial channel and the transient enhanced diffusion suppression, a shallow buried‐channel layer was realized. It is shown that there is an optimal thickness of the buried‐channel layer that maximizes the drain current, and that the Vt stability is higher in the pMOS in which the channel is fabricated by epitaxy than the conventional pMOS fabricated by channel ion implantation. When the gate poly‐Si and the silicon layer selectively grown on the SD were silicide‐reacted with titanium, a low‐resistance gate electrode with an 0.15‐μm width and the low‐leak SD diffusion layer was realized. From the transistor characteristics obtained in the experiment, the circuit characteristics were simulated. It was found that the delay time of the inverter was 21.5 ps.
  • Editor: New York: Wiley Subscription Services, Inc., A Wiley Company
  • Idioma: Inglês
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