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State of art innovative technique for management of scratchpad memory (scratch)

Tabbassum, Kavita ; Talpur, Shahnawaz ; Khahro, Shahnwaz Farhan

Microprocessors and microsystems, 2019-10, Vol.70, p.31-37 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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  • Título:
    State of art innovative technique for management of scratchpad memory (scratch)
  • Autor: Tabbassum, Kavita ; Talpur, Shahnawaz ; Khahro, Shahnwaz Farhan
  • Assuntos: Access time ; Compilers ; Embedded systems ; Energy conservation ; Energy consumption ; Memory management ; Memory management units ; Microprocessor architecture ; Random sampling ; Reconfigurable cache ; Reference systems ; Scratchpad memory ; Software ; Static random access memory
  • É parte de: Microprocessors and microsystems, 2019-10, Vol.70, p.31-37
  • Descrição: •A new compiler-independent SPM management method is proposed.•SPM management is done through the support of hardware and software.•A random selection module is used to predict the frequently accessed addresses at runtime.•Applications in MiBench & OOPACK on a cycle-accurate ARM926EJ-S simulator are used.•33.5% reduction in energy consumption comparing with all-cache reference system. Software-managed scratchpad memory (Scratch) is a type of SRAM, small in size but comparatively fast. Compared with cache, Scratch inspired the programmer having benefits of the small area, as well as low access time and power saving which results in its wide-ranging uses in embedded processors now-a-days. However, existing scratch management methodologies heavily rely on compilers and profiling. It's very difficult to replace embedded applications due to their reliance on compiler. An advanced technique for the management of scratch memory without the support of compiler is presented in this paper to overcome this difficulty. A hardware random sampling unit that depends on the memory reference locality concept is implemented in order to dynamically detect the addresses accessed more often at runtime. By using the support of a memory management unit (MMU), the software operation handled the rerouting of addresses as well as the resultant data movements. The proposed technique is assessed on some typical embedded applications and the outcomes are matched with the cache reference scheme. The small reduction (<1%) in throughput vs. the reference system on average, results 34.2% decrease in energy consumption in the proposed method.
  • Editor: Kidlington: Elsevier B.V
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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