0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
Nakata, Yohei ; Okumura, Shunsuke ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Information and Media Technologies, 2012, Vol.7(2), pp.544-555Tokyo: Information and Media Technologies Editorial Board
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