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0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

Yang, J.-Y. ; Benaissa, K. ; Crenshaw, D. ; Williams, B. ; Sridhar, S. ; Ai, J. ; Boselli, G. ; Zhao, S. ; Tang, S.-P. ; Mahalingam, N. ; Ashburn, S. ; Madhani, P. ; Blythe, T. ; Shichijo, H.

Digest. International Electron Devices Meeting, 2002, p.667-670

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Título:
0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications
Autor: Yang, J.-Y. ; Benaissa, K. ; Crenshaw, D. ; Williams, B. ; Sridhar, S. ; Ai, J. ; Boselli, G. ; Zhao, S. ; Tang, S.-P. ; Mahalingam, N. ; Ashburn, S. ; Madhani, P. ; Blythe, T. ; Shichijo, H.
Assuntos: Capacitors ; CMOS process ; CMOS technology ; Conductivity ; Degradation ; Impedance ; Inductors ; Isolation technology ; Radio frequency ; System-on-a-chip
É parte de: Digest. International Electron Devices Meeting, 2002, p.667-670
Descrição: This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.
Editor: IEEE
Idioma: Inglês

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