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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Zimmer, Brian ; Venkatesan, Rangharajan ; Shao, Yakun Sophia ; Clemons, Jason ; Fojtik, Matthew ; Jiang, Nan ; Keller, Ben ; Klinefelter, Alicia ; Pinckney, Nathaniel ; Raina, Priyanka ; Tell, Stephen G. ; Zhang, Yanqing ; Dally, William J. ; Emer, Joel S. ; Gray, C. Thomas ; Keckler, Stephen W. ; Khailany, Brucek

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932 [Periódico revisado por pares]

New York: IEEE

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Título:
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Autor: Zimmer, Brian ; Venkatesan, Rangharajan ; Shao, Yakun Sophia ; Clemons, Jason ; Fojtik, Matthew ; Jiang, Nan ; Keller, Ben ; Klinefelter, Alicia ; Pinckney, Nathaniel ; Raina, Priyanka ; Tell, Stephen G. ; Zhang, Yanqing ; Dally, William J. ; Emer, Joel S. ; Gray, C. Thomas ; Keckler, Stephen W. ; Khailany, Brucek
Assuntos: Accelerators ; Artificial neural networks ; Bandwidth ; Computer architecture ; Convolution ; Data centers ; Deep neural networks (DNNs) ; Energy efficiency ; Energy storage ; ground-referenced signaling (GRS) ; Inference ; inference accelerator ; multi-chip modules ; Multichip modules ; Neural networks ; Power efficiency ; Prototypes ; Signaling ; single-ended signaling ; System on chip ; Tensors
É parte de: IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932
Descrição: Custom accelerators improve the energy efficiency, area efficiency, and performance of deep neural network (DNN) inference. This article presents a scalable DNN accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic chip are optimal for specific network sizes, the proposed architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. Communication energy is minimized with large on-chip distributed weight storage and a hierarchical network-on-chip and network-on-package, and inference energy is minimized through extensive data reuse. The 16-nm prototype achieves 1.29-TOPS/mm 2 area efficiency, 0.11 pJ/op (9.5 TOPS/W) energy efficiency, 4.01-TOPS peak performance for a one-chip system, and 127.8 peak TOPS and 1903 images/s ResNet-50 batch-1 inference for a 36-chip system.
Editor: New York: IEEE
Idioma: Inglês

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

New York: IEEE

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