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Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

Yeon, Jaewoong ; Yang, Seung-Jun ; Kim, Cheolho ; Lee, Hanho

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13(5), 53, pp.465-472

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Título:
Low-Complexity Triple-Error-Correcting Parallel BCH Decoder
Autor: Yeon, Jaewoong ; Yang, Seung-Jun ; Kim, Cheolho ; Lee, Hanho
Assuntos: 전기공학
É parte de: JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13(5), 53, pp.465-472
Notas: KISTI1.1003/JNL.JAKO201333363223803
G704-002163.2013.13.5.013
Descrição: This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.
Editor: 대한전자공학회
Idioma: Inglês;Coreano

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