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Approach to design a compact reversible low power binary comparator

Hasan Babu, Hafiz Md ; Saleheen, Nazir ; Jamal, Lafifa ; Sarwar, Sheikh Muhammad ; Sasao, Tsutomu

IET computers & digital techniques, 2014-05, Vol.8 (3), p.129-139 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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Título:
Approach to design a compact reversible low power binary comparator
Autor: Hasan Babu, Hafiz Md ; Saleheen, Nazir ; Jamal, Lafifa ; Sarwar, Sheikh Muhammad ; Sasao, Tsutomu
Assuntos: Algorithms ; ancilla input ; Applied sciences ; Babu‐Jamal‐Saleheen‐Sarwar gates ; bit loss recovering ; compact reversible low power n‐bit binary comparator design ; Comparators ; comparators (circuits) ; Computer simulation ; delay ; Design engineering ; digital logic design ; Electrical engineering. Electrical power engineering ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Garbage ; garbage outputs ; Gates (circuits) ; Hasan‐Laflfa‐Nazir‐Sheikh gates ; input‐output mapping ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic ; logic design ; logic gates ; performance evaluation ; power aware computing ; Power consumption ; power consumption reducing ; Power electronics, power supplies ; quantum cost ; reversible gates ; reversible logic ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
É parte de: IET computers & digital techniques, 2014-05, Vol.8 (3), p.129-139
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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Descrição: Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input–output mapping. In this study, the authors propose a reversible low power n-bit binary comparator. An algorithm is presented for constructing a compact reversible n-bit binary comparator circuit. The authors also propose two new reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to optimise the comparator. In addition, several theorems on the numbers of gates, garbage outputs, quantum cost, ancilla input, power, delay and area of the reversible n-bit comparator have been presented. The simulation results of the proposed comparator show that the circuit works correctly and gives significantly better performance than the existing ones. The comparative study shows that, as an example, for a 64-bit comparator, the proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and 3.43% in terms of power over the existing best one. Area and power analysis also show that the proposed design is the most compact as well as a low power circuit.
Editor: Stevenage: The Institution of Engineering and Technology
Idioma: Inglês

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Approach to design a compact reversible low power binary comparator

Hasan Babu, Hafiz Md ; Saleheen, Nazir ; Jamal, Lafifa ; Sarwar, Sheikh Muhammad ; Sasao, Tsutomu

Stevenage: The Institution of Engineering and Technology

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