Idioma:

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

Pham, D.C. ; Aipperspach, T. ; Boerstler, D. ; Bolliger, M. ; Chaudhry, R. ; Cox, D. ; Harvey, P. ; Harvey, P.M. ; Hofstee, H.P. ; Johns, C. ; Kahle, J. ; Kameyama, A. ; Keaty, J. ; Masubuchi, Y. ; Pham, M. ; Pille, J. ; Posluszny, S. ; Riley, M. ; Stasiak, D.L. ; Suzuoki, M. ; Takahashi, O. ; Warnock, J. ; Weitzel, S. ; Wendel, D. ; Yazawa, K.

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.179-196 [Periódico revisado por pares]

New York, NY: IEEE

Texto completo disponível

Citações Citado por

Enviar para

Título:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
Autor: Pham, D.C. ; Aipperspach, T. ; Boerstler, D. ; Bolliger, M. ; Chaudhry, R. ; Cox, D. ; Harvey, P. ; Harvey, P.M. ; Hofstee, H.P. ; Johns, C. ; Kahle, J. ; Kameyama, A. ; Keaty, J. ; Masubuchi, Y. ; Pham, M. ; Pille, J. ; Posluszny, S. ; Riley, M. ; Stasiak, D.L. ; Suzuoki, M. ; Takahashi, O. ; Warnock, J. ; Weitzel, S. ; Wendel, D. ; Yazawa, K.
Assuntos: 90-nm SOI ; Applied sciences ; Architecture ; Bus interface controller (BIC) ; cell processor ; Circuit design ; Circuit synthesis ; Circuits ; Clocks ; Computer architecture ; Control systems ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; element interconnect bus (EIB) ; Exact sciences and technology ; flexible IO ; Hardware ; hardware content protection ; Input-output equipment ; Integrated circuit interconnections ; Integrated circuits ; Linux ; local store ; media-centric computing ; memory interface controller (MIC) ; Microprocessors ; Modularity ; multi-core ; natural human interaction ; Operating systems ; Power Architecture ; power processor element (PPE) ; Power system protection ; Process design ; real-time system ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; simultaneous multi-threading ; SoC ; synergistic processor ; Thermal management ; virtualization
É parte de: IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.179-196
Notas: ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ObjectType-Article-2
ObjectType-Feature-1
Descrição: This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.
Editor: New York, NY: IEEE
Idioma: Inglês

Links

View record in Pascal Francis

Voltar para lista de resultados

Anterior Resultado 5 Avançar Ir para próxima página

Realização: Logos de Redes Sociais:

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

New York, NY: IEEE

Buscando em bases de dados remotas. Favor aguardar.