A CAD methodology for optimizing transistor current and sizing in analog CMOS design

Binkley, D.M. ; Hopper, C.E. ; Tucker, S.D. ; Moss, B.C. ; Rochelle, J.M. ; Foty, D.P.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-02, Vol.22 (2), p.225-237 [Periódico revisado por pares]

New York: IEEE

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