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An ultra low-power hardware accelerator for automatic speech recognition

Yazdani, Reza ; Segura, Albert ; Arnau, Jose-Maria ; Gonzalez, Antonio

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

IEEE

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Título:
An ultra low-power hardware accelerator for automatic speech recognition
Autor: Yazdani, Reza ; Segura, Albert ; Arnau, Jose-Maria ; Gonzalez, Antonio
Assuntos: Acoustic beams ; Acoustics ; Arquitectura de computadors ; Automatic speech recognition ; Enginyeria de la telecomunicació ; Graphics processing units ; Hardware ; Informàtica ; Microprocessadors ; Microprocessor chips ; Microprocessors ; Parallel architectures ; Parallel processing (Electronic computers) ; Power aware computing ; Power consumption ; Processament de la parla ; Processament de la parla i del senyal acústic ; Processament del senyal ; Processament en paral·lel (Ordinadors) ; Search problems ; Speech ; Speech recognition ; Storage management ; Viterbi algorithm ; Àrees temàtiques de la UPC
É parte de: 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12
Descrição: Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems, while delivering high-performance. In this paper, we present an accelerator for large-vocabulary, speaker-independent, continuous speech recognition. It focuses on the Viterbi search algorithm, that represents the main bottleneck in an ASR system. The proposed design includes innovative techniques to improve the memory subsystem, since memory is identified as the main bottleneck for performance and power in the design of these accelerators. We propose a prefetching scheme tailored to the needs of an ASR system that hides main memory latency for a large fraction of the memory accesses with a negligible impact on area. In addition, we introduce a novel bandwidth saving technique that removes 20% of the off-chip memory accesses issued during the Viterbi search. The proposed design outperforms software implementations running on the CPU by orders of magnitude and achieves 1.7x speedup over a highly optimized CUDA implementation running on a high-end Geforce GTX 980 GPU, while reducing by two orders of magnitude (287x) the energy required to convert the speech into text.
Editor: IEEE
Idioma: Inglês

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An ultra low-power hardware accelerator for automatic speech recognition

Yazdani, Reza ; Segura, Albert ; Arnau, Jose-Maria ; Gonzalez, Antonio

IEEE

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