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Novel Cascade FPGA Accelerator for Support Vector Machines Classification

Papadonikolakis, M. ; Bouganis, C.

IEEE transaction on neural networks and learning systems, 2012-07, Vol.23 (7), p.1040-1052

New York, NY: IEEE

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Título:
Novel Cascade FPGA Accelerator for Support Vector Machines Classification
Autor: Papadonikolakis, M. ; Bouganis, C.
Assuntos: Algorithmics. Computability. Computer arithmetics ; Applied sciences ; Architecture ; Cascade classifier ; Cascades ; Classification ; Classifiers ; Computer architecture ; Computer science; control theory; systems ; Data processing. List processing. Character string processing ; Devices ; Digital signal processing ; Electronics ; Exact sciences and technology ; field programmable gate array (FPGA) ; Field programmable gate arrays ; Heterogeneity ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Kernel ; Memory organisation. Data processing ; parallel processing ; Random access memory ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Software ; Studies ; Support vector machines ; support vector machines (SVMs) ; Theoretical computing ; Training
É parte de: IEEE transaction on neural networks and learning systems, 2012-07, Vol.23 (7), p.1040-1052
Notas: ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
Descrição: Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.
Editor: New York, NY: IEEE
Idioma: Inglês

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Novel Cascade FPGA Accelerator for Support Vector Machines Classification

Papadonikolakis, M. ; Bouganis, C.

New York, NY: IEEE

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