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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Lin, Zhiting ; Zhan, Honglan ; Li, Xuan ; Peng, Chunyu ; Lu, Wenjuan ; Wu, Xiulong ; Chen, Junning

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320 [Periódico revisado por pares]

New York: IEEE

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Título:
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands
Autor: Lin, Zhiting ; Zhan, Honglan ; Li, Xuan ; Peng, Chunyu ; Lu, Wenjuan ; Wu, Xiulong ; Chen, Junning
Assuntos: Associative memory ; Binary content-addressable memory (BCAM) ; Boolean ; Boolean algebra ; compound Boolean logic operations ; Compounds ; Computation ; Discharges (electric) ; in-memory computing ; Logic ; Logic gates ; Memory management ; Microprocessors ; Ports ; Power consumption ; Random access memory ; Read-only memory devices ; Searching ; Static random access memory ; static random access memory (SRAM) ; ternary content-addressable memory (TCAM)
É parte de: IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320
Descrição: The von Neumann architecture is approaching its limits in terms of scalability and power consumption. In-memory computation is a possible approach to mitigate this limitation. This brief proposes a configurable 8T static random access memory (SRAM) cell with double word lines and three read ports for in-memory computing. In addition to the normal SRAM function, XOR/XNOR and compound Boolean logic operations of three or four operands, such as AND-OR, AND-OR-INVERT, OR-AND, and OR-AND-INVERT, can be performed in one cycle by fully utilizing the three read ports to obtain 13.2-fJ/bit consumption at 0.6 V. The logic operation frequency is 793 MHz at 1.2 V. The proposed SRAM effectively resolves the bottleneck of the existing in-memory computation schemes that only support compound Boolean logic operations with more than two cycles. In addition, the proposed SRAM array scheme can be configured and used as a binary content-addressable memory or a ternary content-addressable memory for searching operations; it achieves 0.24 fJ/search/bit at 0.6 V in the worst case. At 1.2 V, the searching frequency is up to 813 MHz when searching 128 bits with 65-nm technology.
Editor: New York: IEEE
Idioma: Inglês

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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Lin, Zhiting ; Zhan, Honglan ; Li, Xuan ; Peng, Chunyu ; Lu, Wenjuan ; Wu, Xiulong ; Chen, Junning

New York: IEEE

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