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A million spiking-neuron integrated circuit with a scalable communication network and interface

Merolla, Paul A. ; Arthur, John V. ; Alvarez-Icaza, Rodrigo ; Cassidy, Andrew S. ; Sawada, Jun ; Akopyan, Filipp ; Jackson, Bryan L. ; Imam, Nabil ; Guo, Chen ; Nakamura, Yutaka ; Brezzo, Bernard ; Vo, Ivan ; Esser, Steven K. ; Appuswamy, Rathinakumar ; Taba, Brian ; Amir, Arnon ; Flickner, Myron D. ; Risk, William P. ; Manohar, Rajit ; Modha, Dharmendra S.

Science (American Association for the Advancement of Science), 2014-08, Vol.345 (6197), p.668-673 [Peer Reviewed Journal]

Washington: American Association for the Advancement of Science

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Title:
A million spiking-neuron integrated circuit with a scalable communication network and interface
Author: Merolla, Paul A. ; Arthur, John V. ; Alvarez-Icaza, Rodrigo ; Cassidy, Andrew S. ; Sawada, Jun ; Akopyan, Filipp ; Jackson, Bryan L. ; Imam, Nabil ; Guo, Chen ; Nakamura, Yutaka ; Brezzo, Bernard ; Vo, Ivan ; Esser, Steven K. ; Appuswamy, Rathinakumar ; Taba, Brian ; Amir, Arnon ; Flickner, Myron D. ; Risk, William P. ; Manohar, Rajit ; Modha, Dharmendra S.
Subjects: Architecture ; Architecture (computers) ; Artificial neural networks ; Axons ; Brain ; Chips ; Communication networks ; Communications networks ; Computer architecture ; Computer memory ; Computer simulation ; Integrated circuits ; Interfaces ; Mathematical analysis ; Mathematical models ; Memory ; Neural networks ; Neurons ; Real time ; Semiconductors ; Surface water ; Synapses
Is Part Of: Science (American Association for the Advancement of Science), 2014-08, Vol.345 (6197), p.668-673
Notes: ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
Description: Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.
Publisher: Washington: American Association for the Advancement of Science
Language: English

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A million spiking-neuron integrated circuit with a scalable communication network and interface

Washington: American Association for the Advancement of Science

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