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RTL-to-GDS design tools for monolithic 3D ICs

Kim, Jinwoo ; Murali, Gauthaman ; Vanna-iampikul, Pruek ; Lee, Edward ; Kim, Daehyun ; Chaudhuri, Arjun ; Banerjee, Sanmitra ; Chakrabarty, Krishnendu ; Mukhopadhyay, Saibal ; Lim, Sung Kyu

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8

New York, NY, USA: ACM

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Título:
RTL-to-GDS design tools for monolithic 3D ICs
Autor: Kim, Jinwoo ; Murali, Gauthaman ; Vanna-iampikul, Pruek ; Lee, Edward ; Kim, Daehyun ; Chaudhuri, Arjun ; Banerjee, Sanmitra ; Chakrabarty, Krishnendu ; Mukhopadhyay, Saibal ; Lim, Sung Kyu
Assuntos: built-in self test ; carbon nanotube field-effect transistors ; CNFET ; CNTFETs ; design for testability ; Design-for-test ; design-for-test methodologies ; Hardware ; Hardware -- Electronic design automation ; Hardware -- Electronic design automation -- Physical design (EDA) ; Hardware -- Emerging technologies ; Hardware -- Very large scale integration design ; ILV dual-BIST ; integrated circuit design ; integrated circuit testing ; Integrated circuits ; IR-drop ; logic circuitries ; logic design ; low-overhead built-in self-test module ; M3D process design kit ; Monolithic 3D IC ; monolithic 3D ICs ; open source processor ; optimisation ; Optimization ; Physical design (EDA) ; post-route optimization flow ; power-performance-area optimization ; Random access memory ; resistive memory ; RISC-V Rocketcore ; RTL-to-GDS design flow ; RTL-to-GDS design tools ; thermal analysis ; Three-dimensional displays ; three-dimensional integrated circuits ; Two dimensional displays
É parte de: 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8
Descrição: In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool flow is based on commercial 2D tools and smart ways to extend them to conduct M3D design and simulation. We provide a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization. We also conduct IR-drop and thermal analysis on M3D designs to improve the reliability. To enhance the testability of our M3D designs, we develop design-for-test (DFT) methodologies and integrate a low-overhead built-in self-test module into our design for testing inter-layer vias (ILVs) as well as logic circuitries in the individual tiers. Our benchmark design is RISC-V Rocketcore, which is an open source processor. Our experiments show 8.1% of power, 19.6% of wirelength and 55.7% of area savings with M3D designs at iso-performance compared to its 2D counterpart. In addition, our IR-drop and thermal analyses indicate acceptable power and thermal integrity in our M3D design.
Editor: New York, NY, USA: ACM
Idioma: Inglês

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RTL-to-GDS design tools for monolithic 3D ICs

Kim, Jinwoo ; Murali, Gauthaman ; Vanna-iampikul, Pruek ; Lee, Edward ; Kim, Daehyun ; Chaudhuri, Arjun ; Banerjee, Sanmitra ; Chakrabarty, Krishnendu ; Mukhopadhyay, Saibal ; Lim, Sung Kyu

New York, NY, USA: ACM

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