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FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Arul Murugan, C. ; Karthigaikumar, P. ; Sathya Priya, Sridevi

Automatika, 2020-10, Vol.61 (4), p.682-693 [Revista revisada por pares]

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Título:
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
Autor: Arul Murugan, C. ; Karthigaikumar, P. ; Sathya Priya, Sridevi
Materias: AES ; Algorithms ; Cryptography ; decryption ; Encryption ; Hardware ; Optimization ; S-box ; Vedic multiplier
Es parte de: Automatika, 2020-10, Vol.61 (4), p.682-693
Notas: 258406
Descripción: Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.
Editor: Ljubljana: Taylor & Francis
Idioma: Inglés;Croatian

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