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A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

JIPENG LI ; AHN, Gil-Cho ; CHANG, Dong-Young ; MOON, Un-Ku

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.960-969 [Periódico revisado por pares]

New York, NY: IEEE

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Título:
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
Autor: JIPENG LI ; AHN, Gil-Cho ; CHANG, Dong-Young ; MOON, Un-Ku
Assuntos: Algorithmic ADC ; Algorithms ; Applied sciences ; Architecture ; background digital calibration ; Boosting ; Calibration ; Capacitors ; Circuit properties ; Circuits ; Clocks ; CMOS ; CMOS process ; Design. Technologies. Operation analysis. Testing ; Dielectric, amorphous and glass solid devices ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Energy consumption ; Exact sciences and technology ; Integrated circuits ; Linearity ; low power ; low voltage ; Noise levels ; pipelined ADC ; Prototypes ; Sampling ; Sampling methods ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal convertors ; two channel ADC architecture
É parte de: IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.960-969
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.
Editor: New York, NY: IEEE
Idioma: Inglês

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A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

JIPENG LI ; AHN, Gil-Cho ; CHANG, Dong-Young ; MOON, Un-Ku

New York, NY: IEEE

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