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A Vacancy-Interstitial Defect Pair Model for Positive-Bias Temperature Stress-Induced Electron Trapping Transformation in the High- \kappa Gate n-MOSFET

Gu, Chenjie ; Ang, Diing Shenp ; Gao, Yuan ; Gu, Renyuan ; Zhao, Ziqi ; Zhu, Chao

IEEE transactions on electron devices, 2017-06, Vol.64 (6), p.2505-2511 [Periódico revisado por pares]

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Título:
A Vacancy-Interstitial Defect Pair Model for Positive-Bias Temperature Stress-Induced Electron Trapping Transformation in the High- \kappa Gate n-MOSFET
Autor: Gu, Chenjie ; Ang, Diing Shenp ; Gao, Yuan ; Gu, Renyuan ; Zhao, Ziqi ; Zhu, Chao
Assuntos: VO-Oi defect pair');}" >VO-Oi defect pair ; CMOS reliability ; dynamic bias temperature instability (BTI) ; Electron traps ; Energy states ; Hafnium compounds ; k dielectric');}" > high-k dielectric ; Logic gates ; MOSFET circuits ; oxide traps ; Stress ; Threshold voltage
É parte de: IEEE transactions on electron devices, 2017-06, Vol.64 (6), p.2505-2511
Descrição: Recent device reliability studies have observed the shallow-to-deep transformation of electron-trap states under positive-bias temperature stressing. Being two typical types of defects in the high-κ oxide, the oxygen vacancy and oxygen interstitial have been investigated in many simulations, but results have indicated that the corresponding defect levels are either too shallow or too deep and fail to explain the experimental observation. Here, we propose a vacancy-interstitial (V O -O i ) model. By tuning the relative positions of V O and O i , we show that the charge trap level of the defect pair can be adjusted continuously within the HfO 2 bandgap. This allows us to depict a possible atomic picture for understanding the shallow-to-deep transformation of electron trapping.
Editor: IEEE
Idioma: Inglês

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