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1.5-V 10-Ms/s 8-bit Pipeline ADC in 0.13 μm CMOS using metal fringe capacitor

Fuding Ge ; Kellar, S. ; Thomas, B.

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.133-136

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Título:
1.5-V 10-Ms/s 8-bit Pipeline ADC in 0.13 μm CMOS using metal fringe capacitor
Autor: Fuding Ge ; Kellar, S. ; Thomas, B.
Assuntos: Capacitors ; Circuit noise ; CMOS technology ; Digital circuits ; Pipelines ; Power supplies ; Rail to rail inputs ; Signal processing ; Voltage ; Working environment noise
É parte de: APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.133-136
Descrição: This paper presents the design and measured results of a 1.5-V 10-Ms/s 8-bit pipeline ADC in 0.13 mum CMOS technology. Since there is no MiM-cap available in this process, a specially designed metal fringe cap was used instead. The ADC can digitalize multi-channel signals through a timing-multiplexing scheme. It has rail-to-rail full scale analog input signal range capability through a rail-to-rail unity-gain buffer and a single- to differential-ended signal transformation stage. It achieves a DNL of +0.46/-0.39 LSB and INL of +0.62/-0.44 LSB with a power dissipation of 3.75 mW from a single 1.5 V power supply and a silicon area of 600 mum times 1000 mum.
Editor: IEEE
Idioma: Inglês

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