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Kilo-instruction processors: overcoming the memory wall

Cristal, A. ; Santana, O.J. ; Cazorla, F. ; Galluzzi, M. ; Ramirez, T. ; Pericas, M. ; Valero, M.

IEEE MICRO, 2005-05, Vol.25 (3), p.48-57 [Periódico revisado por pares]

Los Alamitos: IEEE

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Título:
Kilo-instruction processors: overcoming the memory wall
Autor: Cristal, A. ; Santana, O.J. ; Cazorla, F. ; Galluzzi, M. ; Ramirez, T. ; Pericas, M. ; Valero, M.
Assuntos: Arquitectura de computadors ; Cache memory ; Cache storage ; Clocks ; Computer memory ; Delay ; Design engineering ; Energy consumption ; Hardware ; in-flight instructions ; Informàtica ; Instruction sets ; Integrated circuit technology ; Integrated circuits ; issue queue ; Kilo-instruction processors ; memory wall ; Memòria ràpida de treball (Informàtica) ; Microarchitecture ; Microprocessadors ; Microprocessors ; Out of order ; Parallel processing (Electronic computers) ; Performance evaluation ; Pipeline processing ; Pipelines ; Processament en paral·lel (Ordinadors) ; Processors ; Random access memory ; Registers ; ROB ; superscalar processors ; Walls ; Àrees temàtiques de la UPC
É parte de: IEEE MICRO, 2005-05, Vol.25 (3), p.48-57
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. However, performance improvements achievable by high-frequency microprocessors have become seriously limited by main-memory access latencies because main-memory speeds have improved at a much slower pace than microprocessor speeds. Its crucial to deal with this performance disparity, commonly known as the memory wall, to enable future high-frequency microprocessors to achieve their performance potential. To overcome the memory wall, we propose kilo-instruction processors-superscalar processors that can maintain a thousand or more simultaneous in-flight instructions. Doing so means designing key hardware structures so that the processor can satisfy the high resource requirements without significantly decreasing processor efficiency or increasing energy consumption.
Editor: Los Alamitos: IEEE
Idioma: Inglês

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Kilo-instruction processors: overcoming the memory wall

Cristal, A. ; Santana, O.J. ; Cazorla, F. ; Galluzzi, M. ; Ramirez, T. ; Pericas, M. ; Valero, M.

Los Alamitos: IEEE

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