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Future challenges of flash memory technologies

Lu, Chih-Yuan ; Hsieh, Kuang-Yeu ; Liu, Rich

Microelectronic engineering, 2009-03, Vol.86 (3), p.283-286 [Revista revisada por pares]

Amsterdam: Elsevier B.V

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Título:
Future challenges of flash memory technologies
Autor: Lu, Chih-Yuan ; Hsieh, Kuang-Yeu ; Liu, Rich
Materias: Applied sciences ; Band-to-band tunneling hot hole ; Bandgap engineered SONOS ; Channel hot electron ; Charge trapping device ; Compound structure devices ; Design. Technologies. Operation analysis. Testing ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Flash memory ; Floating gate ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; NAND ; NOR ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Es parte de: Microelectronic engineering, 2009-03, Vol.86 (3), p.283-286
Notas: SourceType-Scholarly Journals-2
ObjectType-Feature-2
ObjectType-Conference Paper-1
content type line 23
SourceType-Conference Papers & Proceedings-1
ObjectType-Article-3
Descripción: Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.
Editor: Amsterdam: Elsevier B.V
Idioma: Inglés

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Future challenges of flash memory technologies

Lu, Chih-Yuan ; Hsieh, Kuang-Yeu ; Liu, Rich

Amsterdam: Elsevier B.V

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