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0.3- mu m advanced SAINT FET's having asymmetric n/sup +/-layers for ultra-high-frequency GaAs MMIC's

Enoki, T. ; Yamasaki, K. ; Osafune, K. ; Ohwada, K.

IEEE transactions on electron devices, 1988-01, Vol.35 (1), p.18-24 [Periódico revisado por pares]

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Título:
0.3- mu m advanced SAINT FET's having asymmetric n/sup +/-layers for ultra-high-frequency GaAs MMIC's
Autor: Enoki, T. ; Yamasaki, K. ; Osafune, K. ; Ohwada, K.
Assuntos: Electrodes ; FETs ; Gallium arsenide ; Gaussian distribution ; Leakage current ; MMICs ; Parasitic capacitance ; Space technology ; Substrates ; Threshold voltage
É parte de: IEEE transactions on electron devices, 1988-01, Vol.35 (1), p.18-24
Descrição: Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n/sup +/-layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n/sup +/-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3- mu m gate-length FET was realized without an increase of short-channel effects by using an asymmetric n/sup +/-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure.< >
Editor: IEEE
Idioma: Inglês

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