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fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs

Venieris, Stylianos I. ; Bouganis, Christos-Savvas

IEEE transaction on neural networks and learning systems, 2019-02, Vol.30 (2), p.326-342

United States: IEEE

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Título:
fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs
Autor: Venieris, Stylianos I. ; Bouganis, Christos-Savvas
Assuntos: Architectural design ; Artificial intelligence ; Artificial neural networks ; Computational modeling ; Computer architecture ; Convolutional neural networks ; Convolutional neural networks (ConvNets) ; design space exploration (DSE) ; Feature extraction ; Field programmable gate arrays ; field-programmable gate arrays (FPGAs) ; Gate arrays ; Hardware ; Mapping ; Multiple objective analysis ; Neural networks ; Optimization ; parallel reconfigurable architectures ; Performance enhancement ; Quantitative evaluation ; State of the art ; Task analysis
É parte de: IEEE transaction on neural networks and learning systems, 2019-02, Vol.30 (2), p.326-342
Notas: ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
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Descrição: Since neural networks renaissance, convolutional neural networks (ConvNets) have demonstrated a state-of-the-art performance in several emerging artificial intelligence tasks. The deployment of ConvNets in real-life applications requires power-efficient designs that meet the application-level performance needs. In this context, field-programmable gate arrays (FPGAs) can provide a potential platform that can be tailored to application-specific requirements. However, with the complexity of ConvNet models increasing rapidly, the ConvNet-to-FPGA design space becomes prohibitively large. This paper presents fpgaConvNet, an end-to-end framework for the optimized mapping of ConvNets on FPGAs. The proposed framework comprises an automated design methodology based on the synchronous dataflow (SDF) paradigm and defines a set of SDF transformations in order to efficiently navigate the architectural design space. By proposing a systematic multiobjective optimization formulation, the presented framework is able to generate hardware designs that are cooptimized for the ConvNet workload, the target device, and the application's performance metric of interest. Quantitative evaluation shows that the proposed methodology yields hardware designs that improve the performance by up to <inline-formula> <tex-math notation="LaTeX">6.65\times </tex-math></inline-formula> over highly optimized graphics processing unit designs for the same power constraints and achieve up to <inline-formula> <tex-math notation="LaTeX">2.94\times </tex-math></inline-formula> higher performance density compared with the state-of-the-art FPGA-based ConvNet architectures.
Editor: United States: IEEE
Idioma: Inglês

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fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs

Venieris, Stylianos I. ; Bouganis, Christos-Savvas

United States: IEEE

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