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0 to 50 in 4 years: CUIS at Boeing
0 to 50 in 4 years: CUIS at Boeing
Material Type:
Conference Proceeding 		Add to e-Shelf

0 to 50 in 4 years: CUIS at Boeing

Neher, Kevin ; Worsech, Randy

CHI '97 Extended Abstracts on Human Factors in Computing Systems, 1997, p.85-86

New York, NY, USA: ACM

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2
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI
Material Type:
Article 		Add to e-Shelf

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI

Watanabe, Takahiro ; Watanabe, Minoru

Computer architecture news, 2012-12, Vol.40 (5), p.82-86

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3
0.18μm CMOS and beyond
0.18μm CMOS and beyond
Material Type:
Conference Proceeding 		Add to e-Shelf

0.18μm CMOS and beyond

Eaglesham, D. J. Irwin, Mary Jane

Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 1999, p.703-708

New York, NY, USA: ACM

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4
0.5 V CMOS logic delivering 200 million 88 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology
0.5 V CMOS logic delivering 200 million 88 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology
Material Type:
Conference Proceeding 		Add to e-Shelf

0.5 V CMOS logic delivering 200 million 88 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology

Dudek, Volker ; Grube, Reinhard ; Höfflinger, Bernd ; Schau, Michael

International Symposium on Low Power Electronics and Design: Proceedings of the 1998 international symposium on Low power electronics and design; 10-12 Aug. 1998, 1998, p.103-105

New York, NY, USA: ACM

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5
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
Material Type:
Conference Proceeding 		Add to e-Shelf

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Nakata, Yohei ; Okumura, Shunsuke ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.219-224

New York, NY, USA: ACM

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6
0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme
0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme
Material Type:
Conference Proceeding 		Add to e-Shelf

0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

Li, Simon C. ; Cha, Jimmy C.

International Symposium on Low Power Electronics and Design: Proceedings of the 2002 international symposium on Low power electronics and design; 12-14 Aug. 2002, 2002, p.227-232

New York, NY, USA: ACM

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7
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology
Material Type:
Conference Proceeding 		Add to e-Shelf

A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology

Plouchart, Jean-Olivier ; Kim, Jonghae ; Recoules, Hector ; Zamdmer, Noah ; Tan, Yue ; Sherony, Melanie ; Ray, Asit ; Wagner, Lawrence

International Symposium on Low Power Electronics and Design: Proceedings of the 2003 international symposium on Low power electronics and design; 25-27 Aug. 2003, 2003, p.440-442

New York, NY, USA: ACM

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8
A 0.13μm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity
A 0.13μm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity
Material Type:
Conference Proceeding 		Add to e-Shelf

A 0.13μm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity

Li, Minghai ; Yuan, Fei

Proceedings of the 16th ACM Great Lakes symposium on VLSI, 2006, p.63-66

New York, NY, USA: ACM

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9
A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance
A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance
Material Type:
Conference Proceeding 		Add to e-Shelf

A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance

Shah, Nimesh ; Alam, Manaar ; Sahoo, Durga Prasad ; Mukhopadhyay, Debdeep ; Basu, Arindam

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019, p.627-632

New York, NY, USA: ACM

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10
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns
Material Type:
Conference Proceeding 		Add to e-Shelf

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns

Rolíndez, Luis ; Mir, Salvador ; Prenat, Guillaume ; Bounceur, Ahcène

Proceedings of the conference on Design, automation and test in Europe - Volume 1, 2004, p.10706-10706

Washington, DC, USA: IEEE Computer Society

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