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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover assunto: Software remover
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1
10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
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10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Maroof, Naeem ; Bai-Sun Kong

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1193-1203 [Periódico revisado por pares]

IEEE

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2
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
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3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Bhoj, Ajay N. ; Joshi, Rajiv V. ; Jha, Niraj K.

IEEE transactions on very large scale integration (VLSI) systems, 2013-11, Vol.21 (11), p.2094-2105 [Periódico revisado por pares]

New York, NY: IEEE

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3
692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS
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692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS

GOOD, Tim ; BENAISSA, Mohammed

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1753-1757 [Periódico revisado por pares]

New York, NY: Institute of Electrical and Electronics Engineers

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4
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
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81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC

KIM, Donghyun ; KIM, Kwanho ; KIM, Joo-Young ; LEE, Seungjin ; LEE, Se-Joong ; YOO, Hoi-Jun

IEEE transactions on very large scale integration (VLSI) systems, 2009-03, Vol.17 (3), p.370-383 [Periódico revisado por pares]

New York, NY: IEEE

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5
A 0.13- \mu \text CMOS Dynamically Reconfigurable Charge Pump for Electrostatic MEMS Actuation
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A 0.13- \mu \text CMOS Dynamically Reconfigurable Charge Pump for Electrostatic MEMS Actuation

Alameh, Abdul Hafiz ; Nabki, Frederic

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1261-1270 [Periódico revisado por pares]

IEEE

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6
A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator
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A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

Kwon, Chan-Keun ; Kim, Hoonki ; Park, Jongsun ; Kim, Soo-Won

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1184-1188 [Periódico revisado por pares]

New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)

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7
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
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A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

Chung, Ching-Che ; Su, Wei-Siang ; Lo, Chi-Kuang

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.408-412 [Periódico revisado por pares]

New York: IEEE

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8
A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF
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A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF

Zhao, Qiang ; Wu, Yiheng ; Zhao, Xiaojin ; Cao, Yuan ; Chang, Chip-Hong

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1449-1460 [Periódico revisado por pares]

New York: IEEE

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9
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
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A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency

TSAI, Kun-Hung ; LIU, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.80-88 [Periódico revisado por pares]

New York, NY: IEEE

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10
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL
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A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL

Chou, Ming-Han ; Liu, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2474-2478 [Periódico revisado por pares]

New York: IEEE

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