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Refinado por: assunto: Algorithm Design And Analysis remover assunto: Computer Science, Hardware & Architecture remover
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2004-06, Vol.12 (6), p.573-589 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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2
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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3
Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips
Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips
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Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips

Lin, Cliff Chiung-Yu ; Yao-Wen Chang

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-06, Vol.30 (6), p.817-828 [Periódico revisado por pares]

New York: IEEE

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4
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
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Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Ricci, Andrea ; De Munari, Ilaria ; Ciampolini, Paolo

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, p.315-322

IEEE

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5
IIR digital filter design via orthogonal projection of singular perturbational model reduction
IIR digital filter design via orthogonal projection of singular perturbational model reduction
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IIR digital filter design via orthogonal projection of singular perturbational model reduction

Fang, Wang ; Kwan, Hon Keung

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1132-1135

IEEE

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6
Design Automation for Digital Systems
Design Automation for Digital Systems
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Design Automation for Digital Systems

vanCleemput, W M ; Ofek, H

Computer (Long Beach, Calif.), 1984-10, Vol.17 (10), p.114-122 [Periódico revisado por pares]

IEEE

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7
Partitioning and pipelining for performance-constrained hardware/software systems
Partitioning and pipelining for performance-constrained hardware/software systems
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Partitioning and pipelining for performance-constrained hardware/software systems

Bakshi, S. ; Gajski, D.D.

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.419-432 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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8
VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers
VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers
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VHDL-based design and design methodology for reusable high performance direct digital frequency synthesizers

Janiszewski, I. ; Hoppe, B. ; Meuth, H.

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), 2001, p.573-578

IEEE

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9
Efficient timing closure without timing driven placement and routing
Efficient timing closure without timing driven placement and routing
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Efficient timing closure without timing driven placement and routing

Vujkovic, Miodrag ; Wadkins, David ; Swartz, Bill ; Sechen, Carl

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.268-273

New York, NY, USA: ACM

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10
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
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Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips

Roy, Sudip ; Bhattacharya, Bhargab B ; Chakrabarty, Krishnendu

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-11, Vol.29 (11), p.1696-1708 [Periódico revisado por pares]

New York: IEEE

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