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Refinado por: Nome da Publicação: Ieee Transactions On Computers remover assunto: Software remover
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O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform
O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform
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O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform

Ghosh, Surajeet ; Ray, Sanchita Saha

IEEE transactions on computers, 2023-07, Vol.72 (7), p.2080-2093 [Periódico revisado por pares]

IEEE

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2
Hardware-Based Trusted Computing Architectures for Isolation and Attestation
Hardware-Based Trusted Computing Architectures for Isolation and Attestation
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Hardware-Based Trusted Computing Architectures for Isolation and Attestation

Maene, Pieter ; Gotzfried, Johannes ; de Clercq, Ruan ; Muller, Tilo ; Freiling, Felix ; Verbauwhede, Ingrid

IEEE transactions on computers, 2018-03, Vol.67 (3), p.361-374 [Periódico revisado por pares]

New York: IEEE

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3
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems
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A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems

Jiang, Zhe ; Dai, Xiaotian ; Burns, Alan ; Audsley, Neil ; Gu, Zonghua ; Gray, Ian

IEEE transactions on computers, 2023-01, Vol.72 (1), p.29-42 [Periódico revisado por pares]

IEEE

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4
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Periódico revisado por pares]

New York: IEEE

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5
GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation
GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation
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GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation

Zhibin Yu ; Eeckhout, Lieven ; Goswami, Nilanjan ; Tao Li ; John, Lizy K. ; Hai Jin ; Chengzhong Xu ; Junmin Wu

IEEE transactions on computers, 2015-11, Vol.64 (11), p.3153-3166 [Periódico revisado por pares]

New York: IEEE

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6
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
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Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Ahn, Junwhan ; Yoo, Sungjoo ; Choi, Kiyoung

IEEE transactions on computers, 2016-03, Vol.65 (3), p.940-951 [Periódico revisado por pares]

New York: IEEE

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7
A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices
A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices
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A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices

Zhang, Chong ; Li, Songfan ; Song, Yihang ; Meng, Qianhe ; Lu, Li ; Zhu, Hongzi ; Wang, Xin

IEEE transactions on computers, 2024-03, Vol.73 (3), p.747-763 [Periódico revisado por pares]

IEEE

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8
FlinkCL: An OpenCL-Based In-Memory Computing Architecture on Heterogeneous CPU-GPU Clusters for Big Data
FlinkCL: An OpenCL-Based In-Memory Computing Architecture on Heterogeneous CPU-GPU Clusters for Big Data
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FlinkCL: An OpenCL-Based In-Memory Computing Architecture on Heterogeneous CPU-GPU Clusters for Big Data

Chen, Cen ; Li, Kenli ; Ouyang, Aijia ; Li, Keqin

IEEE transactions on computers, 2018-12, Vol.67 (12), p.1765-1779 [Periódico revisado por pares]

New York: IEEE

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9
Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms
Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms
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Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms

Fadlullah, Zubair Md ; Mao, Bomin ; Tang, Fengxiao ; Kato, Nei

IEEE transactions on computers, 2019-06, Vol.68 (6), p.939-950 [Periódico revisado por pares]

New York: IEEE

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10
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection
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A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection

Possa, Paulo Ricardo ; Mahmoudi, Sidi Ahmed ; Harb, Naim ; Valderrama, Carlos ; Manneback, Pierre

IEEE transactions on computers, 2014-10, Vol.63 (10), p.2376-2388 [Periódico revisado por pares]

New York: IEEE

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