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0.1 um n+-InAs-AlSb-InAs HEMT MMIC Technology for Phased-Array Applications
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0.1 um n+-InAs-AlSb-InAs HEMT MMIC Technology for Phased-Array Applications

Lin, C.H. ; Chou, Y.C. ; Lange, M.D. ; Yang, J.M. ; Nishimoto, M.Y. ; Lee, J. ; Nam, P.S. ; Boos, J.B. ; Bennett, B.R. ; Papanicolaou, N.A. ; Tsai, R.S. ; Gutierrez, A.L. ; Barsky, M.E. ; Chin, T.P. ; Wojtowicz, M. ; Lai, R. ; Oki, A.K.

2007 IEEE Compound Semiconductor Integrated Circuits Symposium, 2007, p.1-4

IEEE

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2
0.1 μm In02Al08Sb-InAs HEMT low-noise amplifiers for ultralow-power applications
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0.1 μm In02Al08Sb-InAs HEMT low-noise amplifiers for ultralow-power applications

Chou, C. ; Lange, M.D. ; Bennett, B.R. ; Boos, J.B. ; Yang, J.M. ; Papanicolaou, N.A. ; Lin, C.H. ; Lee, L.J. ; Nam, P.S. ; Gutierrez, A.L. ; Farkas, D.S. ; Tsai, R.S. ; Wojtowicz, M. ; Chin, T.P. ; Oki, A.K.

2007 IEEE International Electron Devices Meeting, 2007, p.617-620

IEEE

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3
1-11 GHz ultra-wideband resistive ring mixer in 0.18-/spl mu/m CMOS technology
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1-11 GHz ultra-wideband resistive ring mixer in 0.18-/spl mu/m CMOS technology

Chang, T. ; Lin, J.

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, 2006, p.4 pp.

IEEE

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4
1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links
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1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links

Daryoush, A.S. ; Zhang, X. ; Lin, J.Y.

1996 IEEE MTT-S International Microwave Symposium Digest, 1996, Vol.2, p.891-894 vol.2

IEEE

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5
A 0-1 control mechanism with partial information for periodic tumour motion classification
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A 0-1 control mechanism with partial information for periodic tumour motion classification

Lin, C J

2010 IEEE International Symposium on Intelligent Control, 2010, p.1281-1286

IEEE

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6
A 0.05pJ/p-mV 5th-derivative pulse generator for full-band IR-UWB transceiver in 0.18µm CMOS
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A 0.05pJ/p-mV 5th-derivative pulse generator for full-band IR-UWB transceiver in 0.18µm CMOS

Wang, X ; Fan, S ; Qin, B ; Lin, L ; Fang, Q ; Zhao, H ; Tang, H ; Liu, J ; Shi, Z ; Wang, A ; Yang, L ; Cheng, Y

2011 IEEE Radio and Wireless Symposium, 2011, p.70-73

IEEE

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7
A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Basker, V S ; Standaert, T ; Kawasaki, H ; Yeh, C ; Maitra, K ; Yamashita, T ; Faltermeier, J ; Adhikari, H ; Jagannathan, H ; Wang, J ; Sunamura, H ; Kanakasabapathy, S ; Schmitz, S ; Cummings, J ; Inada, A ; Lin, C ; Kulkarni, P ; Zhu, Y ; Kuss, J ; Yamamoto, T ; Kumar, A ; Wahl, J ; Yagishita, A ; Edge, L F ; Kim, R H ; Mclellan, E ; Holmes, S J ; Johnson, R C ; Levin, T ; Demarest, J ; Hane, M ; Takayanagi, M ; Colburn, M ; Paruchuri, V K ; Miller, R J ; Bu, H ; Doris, B ; McHerron, D ; Leobandung, E ; O'Neill, J

2010 Symposium on VLSI Technology, 2010, p.19-20

IEEE

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8
A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
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A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

Young, K.K. ; Wu, S.Y. ; Wu, C.C. ; Wang, C.H. ; Lin, C.T. ; Cheng, J.Y. ; Chiang, M. ; Chen, S.H. ; Lo, T.C. ; Chen, Y.S. ; Chen, J.H. ; Chen, L.J. ; Hou, S.Y. ; Law, J.J. ; Chang, T.E. ; Hou, C.S. ; Shih, J. ; Jeng, S.M. ; Hsieh, H.C. ; Ku, Y. ; Yen, T. ; Tao, H. ; Chao, L.C. ; Shue, S. ; Jang, S.M. ; Ong, T.C. ; Yu, C.H. ; Liang, M.S. ; Diaz, C.H. ; Sun, J.Y.C.

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000, p.563-566

IEEE

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9
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction
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A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction

Xue, X. Y. ; Jian, W. X. ; Yang, J. G. ; Xiao, F. J. ; Chen, G. ; Xu, X. L. ; Xie, Y. F. ; Lin, Y. Y. ; Huang, R. ; Zhou, Q. T. ; Wu, J. G.

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.42-43

IEEE

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10
A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction
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A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction

Jinghua Ye ; Gan Guo ; Lin Huang ; Yihui Chen ; Xuefeng Chen ; Zhiliang Hong

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.534-536 Vol.1

IEEE

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