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CMOS BEOL-embedded z-axis accelerometer
CMOS BEOL-embedded z-axis accelerometer
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CMOS BEOL-embedded z-axis accelerometer

Michalik, P ; Sánchez-Chiva, J.M ; Fernández, D ; Madrenas, J

Electronics letters, 2015-05, Vol.51 (11), p.865-867 [Periódico revisado por pares]

The Institution of Engineering and Technology

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2
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

KANG, Uksong ; CHUNG, Hoe-Ju ; LEE, Jae-Wook ; JOO, Han-Sung ; KIM, Woo-Seop ; DONG HYEON JANG ; NAM SEOG KIM ; CHOI, Jung-Hwan ; CHUNG, Tae-Gyeong ; YOO, Jei-Hwan ; JOO SUN CHOI ; KIM, Changhyun ; HEO, Seongmoo ; JUN, Young-Hyun ; PARK, Duk-Ha ; LEE, Hoon ; JIN HO KIM ; AHN, Soon-Hong ; CHA, Soo-Ho ; AHN, Jaesung ; KWON, Dukmin

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119 [Periódico revisado por pares]

New York, NY: IEEE

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3
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design
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ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design

Chae, Hyunsu ; Zhu, Keren ; Mutnury, Bhyrav ; Wallace, Douglas ; Winterberg, Douglas ; de Araujo, Daniel ; Reddy, Jay ; Klivans, Adam ; Pan, David Z.

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-01, Vol.43 (1), p.1-1 [Periódico revisado por pares]

New York: IEEE

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4
Application and Product-Volume-Specific Customization of BEOL Metal Pitch
Application and Product-Volume-Specific Customization of BEOL Metal Pitch
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Application and Product-Volume-Specific Customization of BEOL Metal Pitch

Pagliarini, Samuel N. ; Isgenc, Mehmet Meric ; Martins, Mayler G. A. ; Pileggi, Lawrence

IEEE transactions on very large scale integration (VLSI) systems, 2018-09, Vol.26 (9), p.1627-1636 [Periódico revisado por pares]

New York: IEEE

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5
3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- \mu \text Pitch
3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- \mu \text Pitch
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3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6- \mu \text Pitch

Kondo, Toru ; Takazawa, Naohiro ; Takemoto, Yoshiaki ; Tsukimura, Mitsuhiro ; Saito, Haruhisa ; Kato, Hideki ; Aoki, Jun ; Kobayashi, Kenji ; Suzuki, Shunsuke ; Gomi, Yuichi ; Matsuda, Seisuke ; Tadaki, Yoshitaka

IEEE transactions on electron devices, 2016-01, Vol.63 (1), p.128-137 [Periódico revisado por pares]

IEEE

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6
Embedded Multidie Interconnect Bridge-A Localized, High-Density Multichip Packaging Interconnect
Embedded Multidie Interconnect Bridge-A Localized, High-Density Multichip Packaging Interconnect
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Embedded Multidie Interconnect Bridge-A Localized, High-Density Multichip Packaging Interconnect

Mahajan, Ravi ; Qian, Zhiguo ; Viswanath, Ram S. ; Srinivasan, Sriram ; Aygun, Kemal ; Jen, Wei-Lun ; Sharan, Sujit ; Dhall, Ashish

IEEE transactions on components, packaging, and manufacturing technology (2011), 2019-10, Vol.9 (10), p.1952-1962 [Periódico revisado por pares]

Piscataway: IEEE

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7
Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits
Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits
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Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits

Jain, A. ; Jones, R.E. ; Chatterjee, R. ; Pozder, S.

IEEE transactions on components and packaging technologies, 2010-03, Vol.33 (1), p.56-63 [Periódico revisado por pares]

New York: IEEE

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8
System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs
System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs
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System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Kumar, Sumeet S. ; Aggarwal, Arnica ; Jagtap, Radhika Sanjeev ; Zjajo, Amir ; van Leuken, Rene

IEEE transactions on very large scale integration (VLSI) systems, 2014-07, Vol.22 (7), p.1606-1619 [Periódico revisado por pares]

New York: IEEE

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9
3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
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3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System

Sakuma, Katsuyuki ; Farooq, Mukta ; Andry, Paul ; Cabral, Cyril ; Wassick, Thomas ; McHerron, Dale ; Divakaruni, Rama

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-05, Vol.11 (5), p.875-878 [Periódico revisado por pares]

Piscataway: IEEE

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10
Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects
Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects
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Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

Bing Dang ; Shapiro, M ; Andry, P ; Tsang, C ; Sprogis, E ; Wright, S ; Interrante, M ; Griffith, J ; Truong, V ; Guerin, L ; Liptak, R ; Berger, D ; Knickerbocker, J

IEEE electron device letters, 2010-12, Vol.31 (12), p.1461-1463 [Periódico revisado por pares]

New York, NY: IEEE

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