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Refinado por: Base de dados/Biblioteca: ANTE: Abstracts in New Technology & Engineering remover Nome da Publicação: Microprocessors And Microsystems remover
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Evaluation of low power consumption network on chip routing architecture
Evaluation of low power consumption network on chip routing architecture
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Evaluation of low power consumption network on chip routing architecture

T S, Arulananth ; M, Baskar ; S M, Udhaya Sankar ; Thiagarajan, R. ; G, Arul Dalton ; Rajeshwari, Pasupuleti Raja ; Kumar, Aruru Sai ; A, Suresh

Microprocessors and microsystems, 2021-04, Vol.82, p.103809, Article 103809 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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2
High throughput unified architecture of LEA algorithm for image encryption
High throughput unified architecture of LEA algorithm for image encryption
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High throughput unified architecture of LEA algorithm for image encryption

Mishra, Zeesha ; Nath, Pallab Kumar ; Acharya, Bibhudendra

Microprocessors and microsystems, 2020-10, Vol.78, p.103214, Article 103214 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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3
Floating accumulator architecture
Floating accumulator architecture
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Floating accumulator architecture

Hwang, Yuan-Shin ; Hsu, Wei-Che

Microprocessors and microsystems, 2017-06, Vol.51, p.8-17 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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4
Enhancing image processing architecture using deep learning for embedded vision systems
Enhancing image processing architecture using deep learning for embedded vision systems
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Enhancing image processing architecture using deep learning for embedded vision systems

Udendhran, R. ; Balamurugan, M. ; Suresh, A. ; Varatharajan, R.

Microprocessors and microsystems, 2020-07, Vol.76, p.103094, Article 103094 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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5
An area-efficient architecture for finite field inversion over GF(2m) using polynomial basis
An area-efficient architecture for finite field inversion over GF(2m) using polynomial basis
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An area-efficient architecture for finite field inversion over GF(2m) using polynomial basis

Nadikuda, Pradeep Kumar Goud ; Boppana, Lakshmi

Microprocessors and microsystems, 2022-03, Vol.89, p.104439, Article 104439 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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6
Street architecture landscape design based on Wireless Internet of Things and GIS system
Street architecture landscape design based on Wireless Internet of Things and GIS system
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Street architecture landscape design based on Wireless Internet of Things and GIS system

Kang, Lin

Microprocessors and microsystems, 2021-02, Vol.80, p.1 [Periódico revisado por pares]

Kidlington: Elsevier BV

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7
An area-time efficient point-multiplication architecture for ECC over GF(2m) using polynomial basis
An area-time efficient point-multiplication architecture for ECC over GF(2m) using polynomial basis
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An area-time efficient point-multiplication architecture for ECC over GF(2m) using polynomial basis

Nadikuda, Pradeep Kumar Goud ; Boppana, Lakshmi

Microprocessors and microsystems, 2022-06, Vol.91, p.104525, Article 104525 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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8
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features
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Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features

Belakhdar, Ibtissem ; Kaaniche, Walid ; Djemal, Ridha ; Ouni, Bouraoui

Microprocessors and microsystems, 2018-04, Vol.58, p.13-23 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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9
A fast and scalable architecture to run convolutional neural networks in low density FPGAs
A fast and scalable architecture to run convolutional neural networks in low density FPGAs
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A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Véstias, Mário P. ; Duarte, Rui P. ; de Sousa, José T. ; Neto, Horácio C.

Microprocessors and microsystems, 2020-09, Vol.77, p.103136, Article 103136 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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10
An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices
An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices
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An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices

Mageswari, N. ; Mahadevan, K. ; Kumar, R. Mohan

Microprocessors and microsystems, 2019-11, Vol.71, p.102855, Article 102855 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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