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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel
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Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel

Shadangi, Ashish Ranjan ; Das, Suvra Sekhar ; Chakrabarti, Indrajit

IEEE transactions on very large scale integration (VLSI) systems, 2024-07, Vol.32 (7), p.1285-1296 [Periódico revisado por pares]

New York: IEEE

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2
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision
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A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision

Zhou, Zikang ; Duan, Xuyang ; Han, Jun

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, p.1-13 [Periódico revisado por pares]

IEEE

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3
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning

Zheng, Xin ; Cheng, Mingjun ; Chen, Jiasong ; Gao, Huaien ; Xiong, Xiaoming ; Cai, Shuting

IEEE transactions on very large scale integration (VLSI) systems, 2024-05, Vol.32 (5), p.860-869 [Periódico revisado por pares]

New York: IEEE

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4
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
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HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization

Dai, Yuan ; Li, Jingyuan ; Zhu, Qilong ; Qiu, Yunhui ; Hu, Yihan ; Yin, Wenbo ; Wang, Lingli

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.505-518 [Periódico revisado por pares]

New York: IEEE

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5
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
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Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection

Rahman, Md Moshiur ; Bhunia, Swarup

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.333-346 [Periódico revisado por pares]

New York: IEEE

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6
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers
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Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

Loh, Johnson ; Gemmeke, Tobias

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.68-78 [Periódico revisado por pares]

New York: IEEE

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7
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash
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Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

Li, Chao ; Sun, Chen ; Yang, Jianyi ; Ni, Kai ; Gong, Xiao ; Zhuo, Cheng ; Yin, Xunzhao

IEEE transactions on very large scale integration (VLSI) systems, 2024, p.1-9 [Periódico revisado por pares]

IEEE

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8
Synthesis of Approximate Parallel-Prefix Adders
Synthesis of Approximate Parallel-Prefix Adders
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Synthesis of Approximate Parallel-Prefix Adders

Stefanidis, Apostolos ; Zoumpoulidou, Ioanna ; Filippas, Dionysios ; Dimitrakopoulos, Giorgos ; Sirakoulis, Georgios Ch

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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9
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
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Microarchitecture Design Space Exploration via Pareto-Driven Active Learning

Zhai, Jianwang ; Cai, Yici

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1727-1739 [Periódico revisado por pares]

New York: IEEE

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10
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration

Sa, Bruno ; Valente, Luca ; Martins, Jose ; Rossi, Davide ; Benini, Luca ; Pinto, Sandro

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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