Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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Material Type: Artigo
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Analysis and simulation of multiplexed single-bus networks with and without bufferingLlabería Griñó, José M. ; Cortés, Mateo Valero ; Lillo, Enrique Herrada ; Mancho, Jesús LabartaComputer architecture news, 1985-06, Vol.13 (3), p.414-421Institute of Electrical and Electronics Engineers (IEEE)Texto completo disponível |
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Material Type: Artigo
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Computing size-independent matrix problems on systolic array processorsNavarro, J. J. ; Llaberia, J. M. ; Valero, M.Computer architecture news, 1986-06, Vol.14 (2), p.271-278Institute of Electrical and Electronics Engineers (IEEE)Texto completo disponível |
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Material Type: Ata de Congresso
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Increasing the number of strides for conflict-free vector accessValero, Mateo ; Lang, Tomás ; Llabería, José M. ; Peiron, Montse ; Ayguadé, Eduard ; Navarra, Juan J.Computer architecture news, 1992, Vol.20 (2), p.372-381Texto completo disponível |
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Material Type: Ata de Congresso
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Hypernode reduction modulo schedulingLlosa, J. ; Valero, M. ; Ayguade, E. ; Gonzalez, A.Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995, p.350-360IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Heuristics for register-constrained software pipeliningLlosa, J. ; Valero, M. ; Ayguade, E.Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29, 1996, p.250-261IEEETexto completo disponível |
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Material Type: Ata de Congresso
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The design and performance of a conflict-avoiding cacheTopham, N. ; Gonzalez, A. ; Gonzalez, J.Proceedings of 30th Annual International Symposium on Microarchitecture, 1997, p.71-80IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Out-of-order vector architecturesEspasa, R. ; Valero, M. ; Smith, J.E.Proceedings of 30th Annual International Symposium on Microarchitecture, 1997, p.160-170IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Effective usage of vector registers in advanced vector architecturesVilla, L. ; Espasa, R. ; Valero, M.Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques, 1997, p.250-260IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Static locality analysis for cache managementSanchez, F.J. ; Gonzalez, A. ; Velero, M.Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques, 1997, p.261-271IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Fast, accurate and flexible data locality analysisSanchez, J. ; Gonzalez, A.Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998, p.124-129IEEETexto completo disponível |